Search Results - "Daly, Jr. George W" :: K.UTB vyhledávací portál

Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration engines

by McDonald Joseph G, Blaner Bartholomew, Daly, Jr. George W, Bass Brian M, Leavens Ross B, Derby Jeffrey H
Year of Publication 18.07.2017

Get full text

Patent

Loading…

Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration engines

by McDonald Joseph G, Blaner Bartholomew, Daly, Jr. George W, Bass Brian M, Leavens Ross B, Derby Jeffrey H
Year of Publication 28.03.2017

Get full text

Patent

Loading…

Method and apparatus for invalidating cache lines during direct memory access (DMA) write operations

by Daly, Jr, George W, Fields, Jr, James S
Year of Publication 31.08.2010

Get full text

Patent

Loading…

Method and apparatus for invalidating cache lines during direct memory access (DMA) write operations

by Daly, Jr, George W, Fields, Jr, James S
Year of Publication 11.11.2008

Get full text

Patent

Loading…

Data processing system and method that permit pipelining of I/O write operations and multiple operation scopes

by Daly, Jr, George W, Fields, Jr, James S, Guthrie, Guy L, Starke, William J, Stuecheli, Jeffrey A
Year of Publication 25.05.2010

Get full text

Patent

Loading…

Method and system for interfacing components of a computing system with a pair of unidirectional, point-to-point buses

by Daly, Jr, George W, Fields, Jr, James S, Grice, Donald G, Heller, Thomas J, Tankeh, Appoloniel N
Year of Publication 28.07.2009

Get full text

Patent

Loading…

Method for interfacing components of a computing system with a pair of unidirectional, point-to-point buses

by Daly, Jr, George W, Fields, Jr, James S, Grice, Donald G, Heller, Jr, Thomas K, Tankeh, Appoloniel N
Year of Publication 14.07.2009

Get full text

Patent

Loading…

Method and apparatus for invalidating entries within a translation control entry (TCE) cache

by Arndt, Richard L, Daly, Jr, George W, Fields, Jr, James S, Maule, Warren E
Year of Publication 11.12.2007

Get full text

Patent

Loading…

Data processing system and method of communication that reduce latency of write transactions subject to retry

by Arimilli, Ravi Kumar, Daly, Jr., George W, Umbarger, Paul
Year of Publication 03.02.2004

Get full text

Patent

Loading…

METHOD, DATA PROCESSING SYSTEM, AND MEMORY CONTROLLER (DATA PROCESSING SYSTEM AND METHOD FOR ENABLING PIPELINING AND MULTIPLE OPERATION SCOPES OF I/O WRITE OPERATION)

by STUECHELI JEFFREY A, DALY GEORGE W JR, FIELDS JAMES S JR, GUY LYNN GUTHRIE, STARKE WILLIAM JOHN
Year of Publication 29.03.2007

Get full text

Patent

Loading…

Data processing system and method that permit pipelining of I/O write operations and multiple operation scopes

by DALY GEORGE W. JR.,FIELDS JAMES S. JR.,GUTHRIE GUY L.,STARKE WILLIAM J.,STUECHELI JEFFREY A
Year of Publication 21.03.2007

Get full text

Patent

Loading…

Accelerated recovery for snooped addresses in a coherent attached processor proxy

by STUECHELI JEFF A, CUMMINGS DAVID W, SIEGEL MICHAEL S, BLANER BARTHOLOMEW, DALY, JR. GEORGE W
Year of Publication 02.02.2016

Get full text

Patent

Loading…

DYNAMICALLY CONFIGURABLE HARDWARE QUEUES FOR DISPATCHING JOBS TO A PLURALITY OF HARDWARE ACCELERATION ENGINES

by MCDONALD JOSEPH G, BASS BRIAN M, LEAVENS ROSS B, BLANER BARTHOLOMEW, DERBY JEFFREY H, DALY, JR. GEORGE W
Year of Publication 10.12.2015

Get full text

Patent

Loading…

DYNAMICALLY CONFIGURABLE HARDWARE QUEUES FOR DISPATCHING JOBS TO A PLURALITY OF HARDWARE ACCELERATION ENGINES

by MCDONALD JOSEPH G, BASS BRIAN M, LEAVENS ROSS B, BLANER BARTHOLOMEW, DERBY JEFFREY H, DALY, JR. GEORGE W
Year of Publication 10.12.2015

Get full text

Patent

Loading…

Accelerated recovery for snooped addresses in a coherent attached processor proxy

by STUECHELI JEFF A, CUMMINGS DAVID W, SIEGEL MICHAEL S, BLANER BARTHOLOMEW, DALY, JR. GEORGE W
Year of Publication 24.03.2015

Get full text

Patent

Loading…

ACCELERATED RECOVERY FOR SNOOPED ADDRESSES IN A COHERENT ATTACHED PROCESSOR PROXY

by STUECHELI JEFF A, CUMMINGS DAVID W, SIEGEL MICHAEL S, BLANER BARTHOLOMEW, DALY, JR. GEORGE W
Year of Publication 17.07.2014

Get full text

Patent

Loading…

ACCELERATED RECOVERY FOR SNOOPED ADDRESSES IN A COHERENT ATTACHED PROCESSOR PROXY

by STUECHELI JEFF A, CUMMINGS DAVID W, SIEGEL MICHAEL S, BLANER BARTHOLOMEW, DALY, JR. GEORGE W
Year of Publication 17.07.2014

Get full text

Patent

Loading…

Method and apparatus for invalidating cache lines during direct memory access (DMA) write operations

by DALY, JR. GEORGE W, FIELDS, JR. JAMES S
Year of Publication 31.08.2010

Get full text

Patent

Loading…

Method and Apparatus for Invalidating Cache Lines During Direct Memory Access (DMA) Write Operations

by DALY, JR. GEORGE W, FIELDS, JR. JAMES S
Year of Publication 27.11.2008

Get full text

Patent

Loading…

Method and apparatus for invalidating cache lines during direct memory access (DMA) write operations

by DALY, JR. GEORGE W, FIELDS, JR. JAMES S
Year of Publication 11.11.2008

Get full text

Patent

Refine Results

Format

Subject Area

Topic

Language

Year of Publication

Database