A solution for an ideal planar multi-gates process for ultimate CMOS?
Monfray, S, Huguenin, J, Martin, M, Samson, M, Borowiak, C, Arvet, C, Dalemcourt, J, Perreau, P, Barnola, S, Bidal, G, Denorme, S, Campidelli, Y, Benotmane, K, Leverd, F, Gouraud, P, Le-Gratiet, B, De-Buttet, C, Pinzelli, L, Beneyton, R, Morel, T, Wacquez, R, Bustos, J, Icard, B, Pain, L, Barraud, S, Ernst, T, Boeuf, F, Faynot, O, Skotnicki, T
Published in 2010 International Electron Devices Meeting (01.12.2010)
Published in 2010 International Electron Devices Meeting (01.12.2010)
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