Design Rule Evaluation Framework Using Automatic Cell Layout Generator for Design Technology Co-Optimization
Jo, Kyeongrok, Ahn, Seyong, Do, Jungho, Song, Taejoong, Kim, Taewhan, Choi, Kyumyung
Published in IEEE transactions on very large scale integration (VLSI) systems (01.08.2019)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.08.2019)
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Journal Article
Analytical Parasitic Resistance and Capacitance Models for Nanosheet Field-Effect Transistors
Suk, JunHa, Kim, YoHan, Do, JungHo, Kim, GaRoom, Baek, SangHoon, Kye, JongWook, Kim, SoYoung
Published in IEEE transactions on electron devices (01.06.2023)
Published in IEEE transactions on electron devices (01.06.2023)
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Journal Article
Breakthrough Design Technology Co-optimization using BSPDN and Standard Cell Variants for Maximizing Block-level PPA
Lee, Seungyoung, Jung, Sungyup, Jang, Yunkyeong, Do, Jungho, Yu, Jisu, You, Hyeoungyu, Jeong, Minjae, Lim, Jinyoung, Han, Jiyun, Park, Sangdo, Kim, Yongdeok, Kwon, Jooyeon, Kim, Hoonki, Yoon, Seiseung
Published in 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (11.06.2023)
Published in 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (11.06.2023)
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Conference Proceeding
An early block type decision method for intra prediction in H.264/AVC
Jungho Do, Sangkwon Na, Chong-Min Kyung
Published in 2009 IEEE Workshop on Signal Processing Systems (01.10.2009)
Published in 2009 IEEE Workshop on Signal Processing Systems (01.10.2009)
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Conference Proceeding