Improving the Detectability of Resistive Open Faults in Scan Cells
Fan Yang, Chakravarty, S., Devta-Prasanna, N., Reddy, S.M., Pomeranz, I.
Published in 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (01.10.2009)
Published in 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (01.10.2009)
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Conference Proceeding
Effective and Efficient Test Pattern Generation for Small Delay Defect
Goel, S.K., Devta-Prasanna, N., Turakhia, R.P.
Published in 2009 27th IEEE VLSI Test Symposium (01.05.2009)
Published in 2009 27th IEEE VLSI Test Symposium (01.05.2009)
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Conference Proceeding
A novel method for fast identification of peak current during test
Wei Zhao, Chakravarty, S., Junxia Ma, Devta-Prasanna, N., Fan Yang, Tehranipoor, M.
Published in 2012 IEEE 30th VLSI Test Symposium (VTS) (01.04.2012)
Published in 2012 IEEE 30th VLSI Test Symposium (VTS) (01.04.2012)
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Conference Proceeding
Accurate measurement of small delay defect coverage of test patterns
Devta-Prasanna, N., Goel, S.K., Gunda, A., Ward, M., Krishnamurthy, P.
Published in 2009 International Test Conference (01.11.2009)
Published in 2009 International Test Conference (01.11.2009)
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Conference Proceeding
Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells
Fan Yang, Chakravarty, S., Devta-Prasanna, N., Reddy, S.M., Pomeranz, I.
Published in 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems (01.10.2008)
Published in 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems (01.10.2008)
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Conference Proceeding