Three-terminal non-volatile multi-state memory for cognitive computing applications
Lee, Yun Seog, Sadana, Devendra K, Brew, Kevin W, Kim, Seyoung, Bedell, Stephen W, Li, Ning, de Souza, Joel P
Year of Publication 18.09.2018
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Year of Publication 18.09.2018
Patent
THREE-TERMINAL NON-VOLATILE MULTI-STATE MEMORY FOR COGNITIVE COMPUTING APPLICATIONS
Lee, Yun Seog, Sadana, Devendra K, Brew, Kevin W, Kim, Seyoung, Bedell, Stephen W, Li, Ning, de Souza, Joel P
Year of Publication 13.09.2018
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Year of Publication 13.09.2018
Patent
Solar cell with interdigitated back contacts formed from high and low work-function-tuned silicides of the same metal
De Souza, Joel P, Sadana, Devendra K, Shahrjerdi, Davood, Hovel, Harold J, Inns, Daniel A, Zhang, Zhen, Kim, Jeehwan, Lavoie, Christian, Saenger, Katherine L
Year of Publication 27.08.2019
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Year of Publication 27.08.2019
Patent
Interface charge reduction for SiGe surface
Sadana, Devendra, Mochizuki, Shogo, Jagannathan, Hemanth, Bedell, Stephen W, Guo, Dechao, Hopstaken, Marinus, Tsutsui, Gen, de Souza, Joel P, Bao, Ruqiang
Year of Publication 13.08.2019
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Year of Publication 13.08.2019
Patent
SELF-ALIGNED SOURCE AND DRAIN REGIONS FOR SEMICONDUCTOR DEVICES
MAURER SIEGFRIED L, HEKMATSHOARTABARI BAHMAN, de SOUZA JOEL P, KIM JEEHWAN, SADANA DEVENDRA K
Year of Publication 27.07.2017
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Year of Publication 27.07.2017
Patent
JUNCTION INTERLAYER DIELECTRIC FOR REDUCING LEAKAGE CURRENT IN SEMICONDUCTOR DEVICES
Sadana Devendra K, de Souza Joel P, Kim Jeehwan, Wacaser Brent A, Fogel Keith E
Year of Publication 22.06.2017
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Year of Publication 22.06.2017
Patent
LOCAL SOI FINS WITH MULTIPLE HEIGHTS
Reznicek Alexander, de Souza Joel P, Cheng Kangguo, Khakifirooz Ali, Schepis Dominic J
Year of Publication 22.06.2017
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Year of Publication 22.06.2017
Patent
Self-aligned source and drain regions for semiconductor devices
Sadana Devendra K, de Souza Joel P, Kim Jeehwan, Hekmatshoartabari Bahman, Maurer Siegfried L
Year of Publication 06.06.2017
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Year of Publication 06.06.2017
Patent
Junction interlayer dielectric for reducing leakage current in semiconductor devices
Sadana Devendra K, de Souza Joel P, Kim Jeehwan, Wacaser Brent A, Fogel Keith E
Year of Publication 16.05.2017
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Year of Publication 16.05.2017
Patent
SEMICONDUCTOR CHIP HAVING TAMPERING FEATURE
Sadana Devendra K, de Souza Joel P, Hekmatshoartabari Bahman, Kuchta Daniel M, Afzali-Ardakani Ali
Year of Publication 27.04.2017
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Year of Publication 27.04.2017
Patent
SEMICONDUCTOR CHIP HAVING TAMPERING FEATURE
Sadana Devendra K, de Souza Joel P, Hekmatshoartabari Bahman, Kuchta Daniel M, Afzali-Ardakani Ali
Year of Publication 27.04.2017
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Year of Publication 27.04.2017
Patent
SEMICONDUCTOR CHIP HAVING TAMPERING FEATURE
Sadana Devendra K, de Souza Joel P, Hekmatshoartabari Bahman, Kuchta Daniel M, Afzali-Ardakani Ali
Year of Publication 27.04.2017
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Year of Publication 27.04.2017
Patent
Doped zinc oxide and n-doping to reduce junction leakage
Sadana Devendra K, de Souza Joel P, Kim Jeehwan, Fogel Keith E, Maurer Siegfried L
Year of Publication 11.04.2017
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Year of Publication 11.04.2017
Patent