Efficient multi-VT FDSOI technology with UTBOX for low power circuit design
Fenouillet-Beranger, C, Thomas, O, Perreau, P, Noel, J.-P, Bajolet, A, Haendler, S, Tosti, L, Barnola, S, Beneyton, R, Perrot, C, de Buttet, C, Abbate, F, Baron, F, Pernet, B, Campidelli, Y, Pinzelli, L, Gouraud, P, Cassé, M, Borowiak, C, Weber, O, Andrieu, F, Denorme, S, Boeuf, F, Faynot, O, Skotnicki, T, Bourdelle, K K, Nguyen, B Y, Boedt, F
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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Conference Proceeding
Impact of a 10 nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32 nm node and below
Fenouillet-Beranger, C., Perreau, P., Denorme, S., Tosti, L., Andrieu, F., Weber, O., Monfray, S., Barnola, S., Arvet, C., Campidelli, Y., Haendler, S., Beneyton, R., Perrot, C., de Buttet, C., Gros, P., Pham-Nguyen, L., Leverd, F., Gouraud, P., Abbate, F., Baron, F., Torres, A., Laviron, C., Pinzelli, L., Vetier, J., Borowiak, C., Margain, A., Delprat, D., Boedt, F., Bourdelle, K., Nguyen, B.-Y., Faynot, O., Skotnicki, T.
Published in Solid-state electronics (01.09.2010)
Published in Solid-state electronics (01.09.2010)
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Conference Proceeding
Impact of a 10nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32nm node and below
Fenouillet-Beranger, C., Perreau, P., Denorme, S., Tosti, L., Andrieu, F., Weber, O., Monfray, S., Barnola, S., Arvet, C., Campidelli, Y., Haendler, S., Beneyton, R., Perrot, C., de Buttet, C., Gros, P., Pham-Nguyen, L., Leverd, F., Gouraud, P., Abbate, F., Baron, F., Torres, A., Laviron, C., Pinzelli, L., Vetier, J., Borowiak, C., Margain, A., Delprat, D., Boedt, F., Bourdelle, K., Nguyen, B.-Y., Faynot, O., Skotnicki, T.
Published in Solid-state electronics (01.09.2010)
Published in Solid-state electronics (01.09.2010)
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Impact of Process Variations on the Capacitance and Electrical Resistance down to 1.44\ \mu\mathrm Hybrid Bonding Interconnects
Ayoub, B., Lhostis, S., Moreau, S., Perez, E. Leon, Jourdon, J., Lamontagne, P., Deloffre, E., Mermoz, S., de Buttet, C., Balan, V., Euvard, C., Exbrayat, Y., Fremont, H.
Published in 2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) (02.12.2020)
Published in 2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) (02.12.2020)
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Conference Proceeding
Optimized emitter-base interface cleaning for advanced Heterojunction Bipolar Transistors
Brezza, E., Deprat, F., de Buttet, C., Gauthier, A., Gregoire, M., Guiheux, D., Guyader, V., Juhel, M., Berbezier, I., Assaf, E., Favre, L., Chevalier, P., Gaquière, C., Defrance, N.
Published in Solid-state electronics (01.06.2023)
Published in Solid-state electronics (01.06.2023)
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Alternative to H3PO4 for Si3N4 Removal by Using Chemical Downstream Etching
de Buttet, Côme, Gourhant, Olivier, Bouyssou, Régis, Zoll, Stephane
Published in ECS transactions (20.02.2015)
Published in ECS transactions (20.02.2015)
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A solution for an ideal planar multi-gates process for ultimate CMOS?
Monfray, S, Huguenin, J, Martin, M, Samson, M, Borowiak, C, Arvet, C, Dalemcourt, J, Perreau, P, Barnola, S, Bidal, G, Denorme, S, Campidelli, Y, Benotmane, K, Leverd, F, Gouraud, P, Le-Gratiet, B, De-Buttet, C, Pinzelli, L, Beneyton, R, Morel, T, Wacquez, R, Bustos, J, Icard, B, Pain, L, Barraud, S, Ernst, T, Boeuf, F, Faynot, O, Skotnicki, T
Published in 2010 International Electron Devices Meeting (01.12.2010)
Published in 2010 International Electron Devices Meeting (01.12.2010)
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Conference Proceeding
UTBOX and ground plane combined with Al2O3 inserted in TiN gate for VT modulation in fully-depleted SOI CMOS transistors
Fenouillet-Beranger, C, Perreau, P, Casse, M, Garros, X, Leroux, C, Martin, F, Gassilloud, R, Bajolet, A, Tosti, L, Barnola, S, Andrieu, F, Weber, O, Beneyton, R, Perrot, C, de Buttet, C, Abbate, F, Pernet, B, Campidelli, Y, Pinzelli, L, Gouraud, P, Huguenin, J L, Borowiak, C, Peru, S, Clement, L, Pantel, R, Bourdelle, K K, Nguyen, B Y, Boedt, F, Denorme, S, Faynot, O, Skotnicki, T, Boeuf, F
Published in Proceedings of 2011 International Symposium on VLSI Technology, Systems and Applications (01.04.2011)
Published in Proceedings of 2011 International Symposium on VLSI Technology, Systems and Applications (01.04.2011)
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Effects of Plasma and Wet Processes on Si-Rich Anti-Reflective Coating to Address Selective Trilayer Rework for Sub-20nm Technology Nodes
Pollet, Olivier, Sommer, Romain, Lachal, Laurent, Barnola, Sebastien, De Buttet, Come, Richard, Claire, Jenny, Cecile
Published in ECS transactions (31.08.2013)
Published in ECS transactions (31.08.2013)
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Journal Article
Parasitic bipolar impact in 32ANBnm undoped channel Ultra-Thin BOX (UTBOX) and biased Ground Plane FDSOI high-k/metal gate technology
Fenouillet-Beranger, C, Perreau, P, Boulenc, P, Tosti, L, Barnola, S, Andrieu, F, Weber, O, Beneyton, R, Perrot, C, de Buttet, C, Abbate, F, Campidelli, Y, Pinzelli, L, Gouraud, P, Margain, A, Peru, S, Bourdelle, K K, Nguyen, B Y, Boedt, F, Poiroux, T, Faynot, O, Skotnicki, T, Boeuf, F
Published in Solid-state electronics (01.08.2012)
Published in Solid-state electronics (01.08.2012)
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Journal Article
Parasitic bipolar impact in 32nm undoped channel Ultra-Thin BOX (UTBOX) and biased Ground Plane FDSOI high-k/metal gate technology
Fenouillet-Beranger, C., Perreau, P., Boulenc, P., Tosti, L., Barnola, S., Andrieu, F., Weber, O., Beneyton, R., Perrot, C., de Buttet, C., Abbate, F., Campidelli, Y., Pinzelli, L., Gouraud, P., Margain, A., Peru, S., Bourdelle, K.K., Nguyen, B.Y., Boedt, F., Poiroux, T., Faynot, O., Skotnicki, T., Boeuf, F.
Published in Solid-state electronics (01.08.2012)
Published in Solid-state electronics (01.08.2012)
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Journal Article
Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below
Fenouillet-Beranger, C., Perreau, P., Denorme, S., Tosti, L., Andrieu, F., Weber, O., Barnola, S., Arvet, C., Campidelli, Y., Haendler, S., Beneyton, R., Perrot, C., de Buttet, C., Gros, P., Pham-Nguyen, L., Leverd, F., Gouraud, P., Abbate, F., Baron, F., Torres, A., Laviron, C., Pinzelli, L., Vetier, J., Borowiak, C., Margain, A., Delprat, D., Boedt, F., Bourdelle, K., Nguyen, B.-Y., Faynot, O., Skotnicki, T.
Published in 2009 Proceedings of the European Solid State Device Research Conference (01.09.2009)
Published in 2009 Proceedings of the European Solid State Device Research Conference (01.09.2009)
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Conference Proceeding
Parasitic bipolar impact in 32nm undoped channel Ultra-Thin BOX (UTBOX) and biased ground plane FDSOI high-k/metal gate technology
Fenouillet-Beranger, C., Perreau, P., Boulenc, P., Tosti, L., Barnola, S., Andrieu, F., Weber, O., Beneyton, R., Perrot, C., de Buttet, C., Abbate, F., Campidelli, Y., Pinzelli, L., Gouraud, P., Margain, A., Peru, S., Bourdelle, K. K., Nguyen, B. Y., Boedt, F., Poiroux, T., Faynot, O., Skotnicki, T., Boeuf, F.
Published in 2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC) (01.09.2011)
Published in 2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC) (01.09.2011)
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Conference Proceeding
Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below
Fenouillet-Beranger, C., Perreau, P., Denorme, S., Tosti, L., Andrieu, F., Weber, O., Barnola, S., Arvet, C., Campidelli, Y., Haendler, S., Beneyton, R., Perrot, C., de Buttet, C., Gros, P., Pham-Nguyen, L., Leverd, F., Gouraud, P., Abbate, F., Baron, F., Torres, A., Laviron, C., Pinzelli, L., Vetier, J., Borowiak, C., Margain, A., Delprat, D., Boedt, F., Bourdelle, K., Nguyen, B.-Y., Faynot, O., Skotnicki, T.
Published in 2009 Proceedings of ESSCIRC (01.09.2009)
Published in 2009 Proceedings of ESSCIRC (01.09.2009)
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Conference Proceeding
A Low Cost Drive Current Enhancement Technique Using Shallow Trench Isolation Induced Stress for 45-nm Node
Le Cam, C., Guyader, F., de Buttet, C., Guyader, P., Ribes, G., Sardo, M., Vanbergue, S., Buf, F., Arnaud, F., Josse, E., Haond, M.
Published in 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers (2006)
Published in 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers (2006)
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A 55 nm triple gate oxide 9 metal layers SiGe BiCMOS technology featuring 320 GHz fT / 370 GHz fMAX HBT and high-Q millimeter-wave passives
Chevalier, P., Avenier, G., Ribes, G., Montagne, A., Canderle, E., Celi, D., Derrier, N., Deglise, C., Durand, C., Quemerais, T., Buczko, M., Gloria, D., Robin, O., Petitdidier, S., Campidelli, Y., Abbate, F., Gros-Jean, M., Berthier, L., Chapon, J. D., Leverd, F., Jenny, C., Richard, C., Gourhant, O., De-Buttet, C., Beneyton, R., Maury, P., Joblot, S., Favennec, L., Guillermet, M., Brun, P., Courouble, K., Haxaire, K., Imbert, G., Gourvest, E., Cossalter, J., Saxod, O., Tavernier, C., Foussadier, F., Ramadout, B., Bianchini, R., Julien, C., Ney, D., Rosa, J., Haendler, S., Carminati, Y., Borot, B.
Published in 2014 IEEE International Electron Devices Meeting (01.12.2014)
Published in 2014 IEEE International Electron Devices Meeting (01.12.2014)
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Conference Proceeding
Hybrid FDSOI/bulk High-k/metal gate platform for low power (LP) multimedia technology
Fenouillet-Beranger, C., Perreau, P., Pham-Nguyen, L., Denorme, S., Andrieu, F., Tosti, L., Brevard, L., Weber, O., Barnola, S., Salvetat, T., Garros, X., Casse, M., Leroux, C., Noel, J.P., Thomas, O., Le-Gratiet, B., Baron, F., Gatefait, M., Campidelli, Y., Abbate, F., Perrot, C., de-Buttet, C., Beneyton, R., Pinzelli, L., Leverd, F., Gouraud, P., Gros-Jean, M., Bajolet, A., Mezzomo, C., Leyris, C., Haendler, S., Noblet, D., Pantel, R., Margain, A., Borowiak, C., Josse, E., Planes, N., Delprat, D., Boedt, F., Bourdelle, K., Nguyen, B.Y., Boeuf, F., Faynot, O., Skotnicki, T.
Published in 2009 IEEE International Electron Devices Meeting (IEDM) (01.12.2009)
Published in 2009 IEEE International Electron Devices Meeting (IEDM) (01.12.2009)
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