Integrated Procedure Automating Test Chip Layout, Place and Route, and Test Plan Development for Efficient Parametric Device and Process Design
Gabrys, A., Greig, W., West, A.J., Lindorfer, P., French, W., Mondal, S., Patra, D., Goswami, K., Sural, S., Crandle, T.
Published in IEEE transactions on semiconductor manufacturing (01.02.2009)
Published in IEEE transactions on semiconductor manufacturing (01.02.2009)
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Journal Article
Monte Carlo modeling of electron transport in repeated overshoot structures
Crandle, T.L., East, J.R., Blakey, P.A.
Published in IEEE transactions on electron devices (01.02.1989)
Published in IEEE transactions on electron devices (01.02.1989)
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Journal Article
PEPPER-a process simulator for VLSI
Mulvaney, B.J., Richardson, W.B., Crandle, T.L.
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.04.1989)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.04.1989)
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Journal Article
A Two-dimensional Process Model For Silicide Growth
Li, C.M., Crandle, T., Temkin, M., Hopper, P.
Published in [Proceedings] 1993 International Workshop on VLSI Process and Device Modeling (1993 VPAD) (1993)
Published in [Proceedings] 1993 International Workshop on VLSI Process and Device Modeling (1993 VPAD) (1993)
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Conference Proceeding
A kinetic model for anomalous diffusion during post-implant annealing
Crandle, T.L., Richardson, W.B., Mulvaney, B.J.
Published in Technical Digest., International Electron Devices Meeting (1988)
Published in Technical Digest., International Electron Devices Meeting (1988)
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Conference Proceeding