Process control & integration options of RMG technology for aggressively scaled devices
Veloso, A., Higuchi, Y., Chew, S. A., Devriendt, K., Ragnarsson, L., Sebaai, F., Schram, T., Brus, S., Vecchio, E., Kellens, K., Rohr, E., Eneman, G., Simoen, E., Cho, M. J., Paraschiv, V., Crabbe, Y., Shi, X., Tielens, H., Van Ammel, A., Dekkers, H., Favia, P., Geypen, J., Bender, H., Phatak, A., del Agua Borniquel, J., Xu, K., Allen, M., Liu, C., Xu, T., Yoo, W. S., Thean, A., Horiguchi, N.
Published in 2012 Symposium on VLSI Technology (VLSIT) (01.06.2012)
Published in 2012 Symposium on VLSI Technology (VLSIT) (01.06.2012)
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Conference Proceeding
High performance Si.45Ge.55 Implant Free Quantum Well FET featuring low temperature process, eSiGe stressor and transversal strain relaxation
Yamaguchi, S., Witters, L., Mitard, J., Eneman, G., Hellings, G., Fukuda, M., Hikavyy, A., Loo, R., Veloso, A., Crabbe, Y., Rohr, E., Favia, P., Bender, H., Takeoka, S., Vellianitis, G., Wang, W., Ragnarsson, L. A., De Meyer, K., Steegen, A., Horiguchi, N.
Published in 2011 International Electron Devices Meeting (01.01.2011)
Published in 2011 International Electron Devices Meeting (01.01.2011)
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Conference Proceeding
Gate-last vs. gate-first technology for aggressively scaled EOT logic/RF CMOS
Veloso, A., Ragnarsson, L.-A, Cho, M. J., Devriendt, K., Kellens, K., Sebaai, F., Suhard, S., Brus, S., Crabbe, Y., Schram, T., Rohr, E., Paraschiv, V., Eneman, G., Kauerauf, T., Dehan, M., Hong, S.-H, Yamaguchi, S., Takeoka, S., Higuchi, Y., Tielens, H., Van Ammel, A., Favia, P., Bender, H., Franquet, A., Conard, T., Li, X., Pey, K.-L, Struyf, H., Mertens, P., Absil, P. P., Horiguchi, N., Hoffmann, T.
Published in 2011 Symposium on VLSI Technology - Digest of Technical Papers (01.06.2011)
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Published in 2011 Symposium on VLSI Technology - Digest of Technical Papers (01.06.2011)
Conference Proceeding
8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS
Witters, L, Takeoka, S, Yamaguchi, S, Hikavyy, A, Shamiryan, D, Cho, M, Chiarella, T, Ragnarsson, L.-A, Loo, R, Kerner, C, Crabbe, Y, Franco, J, Tseng, J, Wang, W E, Rohr, E, Schram, T, Richard, O, Bender, H, Biesemans, S, Absil, P, Hoffmann, T
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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Conference Proceeding
Dual-channel technology with cap-free single metal gate for high performance CMOS in gate-first and gate-last integration
Witters, L., Mitard, J., Veloso, A., Hikavyy, A., Franco, J., Kauerauf, T., Cho, M., Schram, T., Sebai, F., Yamaguchi, S., Takeoka, S., Fukuda, M., Wang, W.-E, Duriez, B., Eneman, G., Loo, R., Kellens, K., Tielens, H., Favia, P., Rohr, E., Hellings, G., Bender, H., Roussel, P., Crabbe, Y., Brus, S., Mannaert, G., Kubicek, S., Devriendt, K., De Meyer, K., Ragnarsson, L.-A, Steegen, A., Horiguchi, N.
Published in 2011 International Electron Devices Meeting (01.12.2011)
Published in 2011 International Electron Devices Meeting (01.12.2011)
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