An 8-b 85-MS/s parallel pipeline A/D converter in 1- mu m CMOS
Conroy, C.S.G., Cline, D.W., Gray, P.R.
Published in IEEE journal of solid-state circuits (01.04.1993)
Published in IEEE journal of solid-state circuits (01.04.1993)
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Journal Article
A 5/sup th/-order continuous-time harmonic-rejection G/sub m/C filter with in-situ calibration for use in transmitter applications
Rudell, J.C., Erdogan, O.E., Yee, D.G., Brockenbrough, R., Conroy, C.S.G., Beomsup Kim
Published in ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005 (2005)
Published in ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005 (2005)
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Conference Proceeding
Statistical design techniques for D/A converters
Conroy, C.S.G., Lane, W.A., Moran, M.A.
Published in IEEE journal of solid-state circuits (01.08.1989)
Published in IEEE journal of solid-state circuits (01.08.1989)
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Journal Article
A high-speed parallel pipelined ADC technique in CMOS
Conroy, C.S.G., Cline, D.W., Gray, P.R.
Published in 1992 Symposium on VLSI Circuits Digest of Technical Papers (1992)
Published in 1992 Symposium on VLSI Circuits Digest of Technical Papers (1992)
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Conference Proceeding
Design considerations for low-power, high-speed CMOS analog/digital converters
Cho, T.B., Cline, D.W., Conroy, C.S.G., Gray, P.R.
Published in Proceedings of 1994 IEEE Symposium on Low Power Electronics (1994)
Published in Proceedings of 1994 IEEE Symposium on Low Power Electronics (1994)
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Conference Proceeding
Statistical Modeling and Simulation for DAC Design
Conroy, C.S.G., Lane, W.A.
Published in ESSCIRC '86: Twelfth European Solid-State Circuits Conference (01.09.1986)
Published in ESSCIRC '86: Twelfth European Solid-State Circuits Conference (01.09.1986)
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Conference Proceeding