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METHOD OF FABRICATING DUAL DAMASCENE STRUCTURE

METHOD OF FABRICATING DUAL DAMASCENE STRUCTURE

by COLBURN MATTHEW EARL, GOLDFARB DARIO L
Year of Publication 05.07.2007

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Patent

PRÄGEFORM-LITHOGRAPHIE

PRÄGEFORM-LITHOGRAPHIE

by COLBURN, MATTHEW, EARL, WILLSON, CARLTON, GRANT
Year of Publication 15.08.2005

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Patent

STEP AND FLASH IMPRINT LITHOGRAPHY

STEP AND FLASH IMPRINT LITHOGRAPHY

by COLBURN, MATTHEW, EARL, WILLSON, CARLTON, GRANT
Year of Publication 10.08.2005

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Patent

Method to generate airgaps with a template first scheme and a self aligned blockout mask

Method to generate airgaps with a template first scheme and a self aligned blockout mask

by Colburn, Matthew Earl, Edelstein, Daniel C, Nitta, Satya Venkata, Purushothaman, Sampath, Ponth, Shom
Year of Publication 04.01.2011

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Patent

Method to generate airgaps with a template first scheme and a self aligned blockout mask

Method to generate airgaps with a template first scheme and a self aligned blockout mask

by COLBURN MATTHEW EARL, PONTH SHOM, EDELSTEIN DANIEL C, PURUSHOTHAMAN SAMPATH, NITTA SATYA VENKATA
Year of Publication 04.01.2011

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Patent

Step and flash imprint lithography

Step and flash imprint lithography

by Willson, Carlton Grant, Colburn, Matthew Earl
Year of Publication 13.04.2004

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Patent

Step and flash imprint lithography

Step and flash imprint lithography

by COLBURN MATTHEW EARL, WILLSON CARLTON GRANT
Year of Publication 13.04.2004

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Patent

INTERCONNECT STRUCTURES WITH PARTIALLY SELF ALIGNED VIAS AND METHODS TO PRODUCE SAME

INTERCONNECT STRUCTURES WITH PARTIALLY SELF ALIGNED VIAS AND METHODS TO PRODUCE SAME

by COLBURN MATTHEW EARL, HUANG ELBERT, NITTA SATYANARAYANA V, FULLER NICHOLAS C
Year of Publication 13.08.2009

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Patent

STEP AND FLASH IMPRINT LITHOGRAPHY

STEP AND FLASH IMPRINT LITHOGRAPHY

by COLBURN, MATTHEW, EARL, WILLSON, CARLTON, GRANT
Year of Publication 07.08.2002

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Patent

STEP AND FLASH IMPRINT LITHOGRAPHY

STEP AND FLASH IMPRINT LITHOGRAPHY

by COLBURN, MATTHEW, EARL, WILLSON, CARLTON, GRANT
Year of Publication 02.05.2002

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Patent

METHOD OF FORMING A DUAL-DAMASCENE STRUCTURE USING AN UNDERLAYER

METHOD OF FORMING A DUAL-DAMASCENE STRUCTURE USING AN UNDERLAYER

by COLBURN MATTHEW EARL, MEDEIROS DAVID R, BURNS SEAN DAVID, PATEL KAUSHAL, VYKLICKY LIBOR, LUSTIG NAFTALI ELIAHU
Year of Publication 09.04.2009

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Patent

Step and flash imprint lithography

Step and flash imprint lithography

by COLBURN MATTHEW EARL, WILLSON CARLTON GRANT
Year of Publication 01.01.2002

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Patent

Step and flash imprint lithography

Step and flash imprint lithography

by Willson, Carlton Grant, Colburn, Matthew Earl
Year of Publication 01.01.2002

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Patent

Step and flash imprint lithography

Step and flash imprint lithography

by COLBURN MATTHEW EARL, WILLSON CARLTON GRANT
Year of Publication 15.11.2001

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Patent

SEMICONDUCTOR AND METHOD OF FORMING AIR GAP IN SEMICONDUCTOR DEVICE (AIR GAP WITH SELECTIVE PINCHOFF USING ANTI-NUCLEATION LAYER)

SEMICONDUCTOR AND METHOD OF FORMING AIR GAP IN SEMICONDUCTOR DEVICE (AIR GAP WITH SELECTIVE PINCHOFF USING ANTI-NUCLEATION LAYER)

by COLBURN MATTHEW EARL, BREYTA GREGORY, CLEVENGER LAWRENCE A, SHOM PONOTH, EDELSTEIN DANIEL C
Year of Publication 13.11.2008

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Patent

Electronics structures using a sacrificial multi-layer hardmask scheme

Electronics structures using a sacrificial multi-layer hardmask scheme

by Colburn, Matthew Earl, Donaton, Ricardo Alves, Murray, Conal E, Nitta, Satyanarayana Venkata, Purushothaman, Sampath, Sankaran, Sujatha, Standaert, Thedorus Eduardos, Liu, Xiao Hu
Year of Publication 24.05.2011

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Patent

Electronics structures using a sacrificial multi-layer hardmask scheme

Electronics structures using a sacrificial multi-layer hardmask scheme

by MURRAY CONAL E, COLBURN MATTHEW EARL, STANDAERT THEDORUS EDUARDOS, NITTA SATYANARAYANA VENKATA, DONATON RICARDO ALVES, SANKARAN SUJATHA, PURUSHOTHAMAN SAMPATH, LIU XIAO HU
Year of Publication 24.05.2011

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Patent

STEP AND FLASH IMPRINT LITHOGRAPHY

STEP AND FLASH IMPRINT LITHOGRAPHY

by COLBURN, MATTHEW, EARL, WILLSON, CARLTON, GRANT
Year of Publication 14.09.2000

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Patent

Electronics Structures Using a Sacrificial Multi-Layer Hardmask Scheme

Electronics Structures Using a Sacrificial Multi-Layer Hardmask Scheme

by MURRAY CONAL E, COLBURN MATTHEW EARL, NITTA SATYANARAYANA VENKATA, DONATON RICARDO ALVES, SANKARAN SUJATHA, STANDAERT THEDORUS EDUARDUS FRANSISCUS MARIA, PURUSHOTHAMAN SAMPATH, LIU XIAO HU
Year of Publication 16.10.2008

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Process for preparing electronics structures using a sacrificial multilayer hardmask scheme

Process for preparing electronics structures using a sacrificial multilayer hardmask scheme

by MURRAY CONAL E, COLBURN MATTHEW EARL, NITTA SATYANARAYANA VENKATA, DONATON RICARDO ALVES, SANKARAN SUJATHA, STANDAERT THEODORUS EDUARDUS FRANSISCUS MARIA, PURUSHOTHAMAN SAMPATH, LIU XIAO HU
Year of Publication 13.05.2008

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Patent