Search Results - "Civay Deniz E" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

Artificial Protein Block Copolymers Blocks Comprising Two Distinct Self-Assembling Domains

Artificial Protein Block Copolymers Blocks Comprising Two Distinct Self-Assembling Domains

by Haghpanah, Jennifer S, Yuvienco, Carlo, Civay, Deniz E, Barra, Hanna, Baker, Peter J, Khapli, Sachin, Voloshchuk, Natalya, Gunasekar, Susheel K, Muthukumar, Murugappan, Montclare, Jin K
Published in Chembiochem : a European journal of chemical biology (23.11.2009)

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Journal Article

Automated redesign of integrated circuits using relaxed spacing rules

Automated redesign of integrated circuits using relaxed spacing rules

by Laffosse, Elise, Civay, Deniz E
Year of Publication 04.02.2020

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Patent

AUTOMATED REDESIGN OF INTEGRATED CIRCUITS USING RELAXED SPACING RULES

AUTOMATED REDESIGN OF INTEGRATED CIRCUITS USING RELAXED SPACING RULES

by Laffosse, Elise, Civay, Deniz E
Year of Publication 18.07.2019

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Patent

Test pattern for feature cross-sectioning

Test pattern for feature cross-sectioning

by SCHLIEF RALPH, CIVAY DENIZ E
Year of Publication 19.07.2016

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Patent

TEST PATTERN FOR FEATURE CROSS-SECTIONING

TEST PATTERN FOR FEATURE CROSS-SECTIONING

by SCHLIEF RALPH, CIVAY DENIZ E
Year of Publication 31.12.2015

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Patent

Self-aligned conductive polymer pattern placement error compensation layer

Self-aligned conductive polymer pattern placement error compensation layer

by Hosler Erik R, Civay Deniz E
Year of Publication 05.09.2017

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Patent

Pattern placement error compensation layer in via opening

Pattern placement error compensation layer in via opening

by Hosler Erik R, Civay Deniz E
Year of Publication 29.08.2017

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Patent

Automated redesign of integrated circuits using relaxed spacing rules

Automated redesign of integrated circuits using relaxed spacing rules

by CIVAY, DENIZ E, LAFFOSSE, ELISE
Year of Publication 01.12.2020

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Patent

Pattern placement error compensation layer

Pattern placement error compensation layer

by Hosler Erik R, Civay Deniz E
Year of Publication 11.07.2017

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Patent

PATTERN PLACEMENT ERROR COMPENSATION LAYER

PATTERN PLACEMENT ERROR COMPENSATION LAYER

by Hosler Erik R, Civay Deniz E
Year of Publication 18.05.2017

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Patent

PATTERN PLACEMENT ERROR COMPENSATION LAYER IN VIA OPENING

PATTERN PLACEMENT ERROR COMPENSATION LAYER IN VIA OPENING

by Hosler Erik R, Civay Deniz E
Year of Publication 18.05.2017

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Patent

SELF-ALIGNED CONDUCTIVE POLYMER PATTERN PLACEMENT ERROR COMPENSATION LAYER

SELF-ALIGNED CONDUCTIVE POLYMER PATTERN PLACEMENT ERROR COMPENSATION LAYER

by Hosler Erik R, Civay Deniz E
Year of Publication 18.05.2017

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Patent

CONDUCTIVELY DOPED POLYMER PATTERN PLACEMENT ERROR COMPENSATION LAYER

CONDUCTIVELY DOPED POLYMER PATTERN PLACEMENT ERROR COMPENSATION LAYER

by Hosler Erik R, Civay Deniz E
Year of Publication 18.05.2017

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Patent

Conductively doped polymer pattern placement error compensation layer

Conductively doped polymer pattern placement error compensation layer

by Hosler Erik R, Civay Deniz E
Year of Publication 25.04.2017

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Patent

Automated redesign of integrated circuits using relaxed spacing rules

Automated redesign of integrated circuits using relaxed spacing rules

by CIVAY, DENIZ E, LAFFOSSE, ELISE
Year of Publication 16.08.2019

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Patent

Fully depleted silicon-on-insulator (FDSOI) transistor device and self-aligned active area in FDSOI bulk exposed regions

Fully depleted silicon-on-insulator (FDSOI) transistor device and self-aligned active area in FDSOI bulk exposed regions

by Nayyar, Neha, Luning, Scott D, Pritchard, David, Civay, Deniz E, Lei, Lixia
Year of Publication 22.01.2019

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Patent

FULLY DEPLETED SILICON-ON-INSULATOR (FDSOI) TRANSISTOR DEVICE AND SELF-ALIGNED ACTIVE AREA IN FDSOI BULK EXPOSED REGIONS

FULLY DEPLETED SILICON-ON-INSULATOR (FDSOI) TRANSISTOR DEVICE AND SELF-ALIGNED ACTIVE AREA IN FDSOI BULK EXPOSED REGIONS

by LEI, Lixia, NAYYAR, Neha, LUNING, Scott D, PRITCHARD, David, CIVAY, Deniz E
Year of Publication 12.07.2018

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Patent

Fully depleted silicon-on-insulator (FDSOI) transistor device and self-aligned active area in FDSOI bulk exposed regions

Fully depleted silicon-on-insulator (FDSOI) transistor device and self-aligned active area in FDSOI bulk exposed regions

by Luning Scott D, Civay Deniz E, Lei Lixia, Pritchard David, Nayyar Neha
Year of Publication 10.04.2018

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Patent