A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs
Pei-Wen Luo, Chi-Kang Chen, Yu-Hui Sung, Wei Wu, Hsiu-Chuan Shih, Chia-Hsin Lee, Kuo-Hua Lee, Ming-Wei Li, Mei-Chiang Lung, Chun-Nan Lu, Yung-Fa Chou, Po-Lin Shih, Chung-Hu Ke, Chun Shiah, Stolt, Patrick, Tomishima, Shigeki, Ding-Ming Kwai, Bor-Doou Rong, Lu, Nicky, Shih-Lien Lu, Cheng-Wen Wu
Published in 2015 Symposium on VLSI Circuits (VLSI Circuits) (01.06.2015)
Published in 2015 Symposium on VLSI Circuits (VLSI Circuits) (01.06.2015)
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Conference Proceeding
Journal Article
BiCMOS performance enhancement by mechanical uniaxial strain and methods of manufacture
Ko, Chih-Hsin, Wang, Tzu-Juei, Chen, Hung-Wei, Ke, Chung-Hu, Lee, Wen-Chin
Year of Publication 28.09.2010
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Year of Publication 28.09.2010
Patent
Hybrid Schottky source-drain CMOS for high mobility and low barrier
Ke, Chung-Hu, Ko, Chih-Hsin, Chen, Hung-Wei, Lee, Wen-Chin, Chi, Min-Hwa
Year of Publication 15.06.2010
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Year of Publication 15.06.2010
Patent