A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits
Lee, Dong Uk, Kim, Kyung Whan, Kim, Kwan Weon, Lee, Kang Seol, Byeon, Sang Jin, Kim, Jae Hwan, Cho, Jin Hee, Lee, Jaejin, Chun, Jun Hyun
Published in IEEE journal of solid-state circuits (01.01.2015)
Published in IEEE journal of solid-state circuits (01.01.2015)
Get full text
Journal Article
A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces
Lee, Hyun-Woo, Choi, Hoon, Shin, Beom-Ju, Kim, Kyung-Hoon, Kim, Kyung-Whan, Kim, Jaeil, Kim, Kwang-Hyun, Jung, Jong-Ho, Kim, Jae-Hwan, Park, Eun-Young, Kim, Jong-Sam, Kim, Jong-Hwan, Cho, Jin-Hee, Rye, Namgyu, Chun, Jun-Hyun, Kim, Yunsaing, Kim, Chulwoo, Choi, Young-Jung, Chung, Byong-Tae
Published in IEEE journal of solid-state circuits (01.06.2012)
Published in IEEE journal of solid-state circuits (01.06.2012)
Get full text
Journal Article
Design considerations of HBM stacked DRAM and the memory architecture extension
Dong Uk Lee, Kang Seol Lee, Yongwoo Lee, Kyung Whan Kim, Jong Ho Kang, Jaejin Lee, Jun Hyun Chun
Published in 2015 IEEE Custom Integrated Circuits Conference (CICC) (01.09.2015)
Published in 2015 IEEE Custom Integrated Circuits Conference (CICC) (01.09.2015)
Get full text
Conference Proceeding
Non-resistance metric based read scheme for multi-level PCRAM in 25 nm technology
Junho Cheon, Insoo Lee, Changyong Ahn, Stanisavljevic, Milos, Athmanathan, Aravinthan, Papandreou, Nikolaos, Pozidis, Haris, Eleftheriou, Evangelos, Minchul Shin, Taekseung Kim, Jong Ho Kang, Jun Hyun Chun
Published in 2015 IEEE Custom Integrated Circuits Conference (CICC) (01.09.2015)
Published in 2015 IEEE Custom Integrated Circuits Conference (CICC) (01.09.2015)
Get full text
Conference Proceeding
High bandwidth memory(HBM) with TSV technique
Jong Chern Lee, Jihwan Kim, Kyung Whan Kim, Young Jun Ku, Dae Suk Kim, Chunseok Jeong, Tae Sik Yun, Hongjung Kim, Ho Sung Cho, Sangmuk Oh, Hyun Sung Lee, Ki Hun Kwon, Dong Beom Lee, Young Jae Choi, Jaejin Lee, Hyeon Gon Kim, Jun Hyun Chun, Jonghoon Oh, Seok Hee Lee
Published in 2016 International SoC Design Conference (ISOCC) (01.10.2016)
Published in 2016 International SoC Design Conference (ISOCC) (01.10.2016)
Get full text
Conference Proceeding
A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface
Hyun-Woo Lee, Yong-Hoon Kim, Won-Joo Yun, Eun Young Park, Kang Youl Lee, Jaeil Kim, Kwang Hyun Kim, Jong Ho Jung, Kyung Whan Kim, Nam Gyu Rye, Kwan-Weon Kim, Jun Hyun Chun, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung, Joong Sik Kih
Published in 2010 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2010)
Published in 2010 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2010)
Get full text
Conference Proceeding
An exact measurement and repair circuit of TSV connections for 128GB/s high-bandwidth memory(HBM) stacked DRAM
Dong Uk Lee, Kyung Whan Kim, Kwan Weon Kim, Kang Seol Lee, Sang Jin Byeon, Jin Hee Cho, Han Ho Jin, Sang Kyun Nam, Jaejin Lee, Jun Hyun Chun, Sungjoo Hong
Published in 2014 Symposium on VLSI Circuits Digest of Technical Papers (01.06.2014)
Published in 2014 Symposium on VLSI Circuits Digest of Technical Papers (01.06.2014)
Get full text
Conference Proceeding
A 10 Gb/s 4-PAM transceiver with adaptive pre-emphasis
Sungmin Yoo, Daeho Yun, Bongsub Song, Jinwook Burm, Jinil Chung, Jun Hyun Chun
Published in 2011 International Symposium on Integrated Circuits (01.12.2011)
Published in 2011 International Symposium on Integrated Circuits (01.12.2011)
Get full text
Conference Proceeding