Integrated Low‐Dimensional Semiconductors for Scalable Low‐power CMOS Logic
Chuang, Meng‐Hsi, Chiu, Kuan‐Chang, Lin, Yu‐Ting, Tulevski, George, Chen, Po‐Han, Pezeshki, Atiye, Chen, Chung‐Jen, Chen, Po‐Yen, Chen, Lih‐Juann, Han, Shu‐Jen, Lee, Yi‐Hsien
Published in Advanced functional materials (01.07.2023)
Published in Advanced functional materials (01.07.2023)
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Synthesis of In‐Plane Artificial Lattices of Monolayer Multijunctions
Chiu, Kuan‐Chang, Huang, Kuan‐Hua, Chen, Chun‐An, Lai, Ying‐Yu, Zhang, Xin‐Quan, Lin, Erh‐Chen, Chuang, Meng‐Hsi, Wu, Jenn‐Ming, Lee, Yi‐Hsien
Published in Advanced materials (Weinheim) (01.02.2018)
Published in Advanced materials (Weinheim) (01.02.2018)
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Journal Article
Scalable Moiré Lattice with Oriented TMD Monolayers
Chuang, Meng-Hsi, Chen, Chun-An, Liu, Po-Yen, Zhang, Xin-Quan, Yeh, Nai-Yu, Shih, Hao-Jen, Lee, Yi-Hsien
Published in Nanoscale research letters (14.03.2022)
Published in Nanoscale research letters (14.03.2022)
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Journal Article
Controlled Low‐Frequency Electrical Noise of Monolayer MoS2 with Ohmic Contact and Tunable Carrier Concentration
Wang, Ji‐Wun, Liu, Yen‐Po, Chen, Po‐Han, Chuang, Meng‐Hsi, Pezeshki, Atiye, Ling, Dah‐Chin, Chen, Jeng‐Chung, Chen, Yung‐Fu, Lee, Yi‐Hsien
Published in Advanced electronic materials (01.01.2018)
Published in Advanced electronic materials (01.01.2018)
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Journal Article
Design, Modeling, and Fabrication of Chemical Vapor Deposition Grown MoS2 Circuits with E‑Mode FETs for Large-Area Electronics
Yu, Lili, El-Damak, Dina, Radhakrishna, Ujwal, Ling, Xi, Zubair, Ahmad, Lin, Yuxuan, Zhang, Yuhao, Chuang, Meng-Hsi, Lee, Yi-Hsien, Antoniadis, Dimitri, Kong, Jing, Chandrakasan, Anantha, Palacios, Tomas
Published in Nano letters (12.10.2016)
Published in Nano letters (12.10.2016)
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Journal Article
Passivated Interfacial Traps of Monolayer MoS2 with Bipolar Electrical Pulse
Chen, Po-Han, Chen, Chun-An, Lin, Yu-Ting, Hsieh, Ping-Yi, Chuang, Meng-Hsi, Liu, Xiaoze, Hsieh, Tung-Ying, Shen, Chang-Hong, Shieh, Jia-Min, Wu, Meng-Chyi, Chen, Yung-Fu, Yang, Chih-Chao, Lee, Yi-Hsien
Published in ACS applied materials & interfaces (01.03.2023)
Published in ACS applied materials & interfaces (01.03.2023)
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Journal Article
Monolayer Multijunctions: Synthesis of In‐Plane Artificial Lattices of Monolayer Multijunctions (Adv. Mater. 7/2018)
Chiu, Kuan‐Chang, Huang, Kuan‐Hua, Chen, Chun‐An, Lai, Ying‐Yu, Zhang, Xin‐Quan, Lin, Erh‐Chen, Chuang, Meng‐Hsi, Wu, Jenn‐Ming, Lee, Yi‐Hsien
Published in Advanced materials (Weinheim) (01.02.2018)
Published in Advanced materials (Weinheim) (01.02.2018)
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Journal Article
Passivated Interfacial Traps of Monolayer MoS 2 with Bipolar Electrical Pulse
Chen, Po-Han, Chen, Chun-An, Lin, Yu-Ting, Hsieh, Ping-Yi, Chuang, Meng-Hsi, Liu, Xiaoze, Hsieh, Tung-Ying, Shen, Chang-Hong, Shieh, Jia-Min, Wu, Meng-Chyi, Chen, Yung-Fu, Yang, Chih-Chao, Lee, Yi-Hsien
Published in ACS applied materials & interfaces (01.03.2023)
Published in ACS applied materials & interfaces (01.03.2023)
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Journal Article
Design, Modeling, and Fabrication of Chemical Vapor Deposition Grown MoS 2 Circuits with E-Mode FETs for Large-Area Electronics
Yu, Lili, El-Damak, Dina, Radhakrishna, Ujwal, Ling, Xi, Zubair, Ahmad, Lin, Yuxuan, Zhang, Yuhao, Chuang, Meng-Hsi, Lee, Yi-Hsien, Antoniadis, Dimitri, Kong, Jing, Chandrakasan, Anantha, Palacios, Tomas
Published in Nano letters (12.10.2016)
Published in Nano letters (12.10.2016)
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Journal Article
Controlled Low‐Frequency Electrical Noise of Monolayer MoS 2 with Ohmic Contact and Tunable Carrier Concentration
Wang, Ji‐Wun, Liu, Yen‐Po, Chen, Po‐Han, Chuang, Meng‐Hsi, Pezeshki, Atiye, Ling, Dah‐Chin, Chen, Jeng‐Chung, Chen, Yung‐Fu, Lee, Yi‐Hsien
Published in Advanced electronic materials (01.01.2018)
Published in Advanced electronic materials (01.01.2018)
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Journal Article
Enabling monolithic 3D image sensor using large-area monolayer transition metal dichalcogenide and logic/memory hybrid 3D+IC
Chih-Chao Yang, Kuan-Chang Chiu, Cheng-Tse Chou, Chang-Ning Liao, Meng-Hsi Chuang, Tung-Ying Hsieh, Wen-Hsien Huang, Chang-Hong Shen, Jia-Min Shieh, Wen-Kuan Yeh, Yu-Hsiu Chen, Meng-Chyi Wu, Yi-Hsien Lee
Published in 2016 IEEE Symposium on VLSI Technology (01.06.2016)
Published in 2016 IEEE Symposium on VLSI Technology (01.06.2016)
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