Turning silicon on its edge [double gate CMOS/FinFET technology]
Nowak, E.J., Aller, I., Ludwig, T., Kim, K., Joshi, R.V., Ching-Te Chuang, Bernstein, K., Puri, R.
Published in IEEE circuits and devices magazine (01.01.2004)
Published in IEEE circuits and devices magazine (01.01.2004)
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Journal Article
The impact of gate-oxide breakdown on SRAM stability
Rodriguez, R., Stathis, J.H., Linder, B.P., Kowalczyk, S., Chuang, C.T., Joshi, R.V., Northrop, G., Bernstein, K., Bhavnagarwala, A.J., Lombardo, S.
Published in IEEE electron device letters (01.09.2002)
Published in IEEE electron device letters (01.09.2002)
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Journal Article
Leakage power analysis of 25-nm double-gate CMOS devices and circuits
Keunwoo Kim, Das, K.K., Joshi, R.V., Ching-Te Chuang
Published in IEEE transactions on electron devices (01.05.2005)
Published in IEEE transactions on electron devices (01.05.2005)
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Journal Article
Novel high-density low-power logic circuit techniques using DG devices
Meng-Hsueh Chiang, Keunwoo Kim, Tretz, C., Ching-Te Chuang
Published in IEEE transactions on electron devices (01.10.2005)
Published in IEEE transactions on electron devices (01.10.2005)
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Journal Article
Optimal UTB FD/SOI device structure using thin BOX for sub-50-nm SRAM design
Mukhopadhyay, S., Keunwoo Kim, Xinlin Wang, Frank, D.J., Oldiges, P., Ching-Te Chuang, Roy, K.
Published in IEEE electron device letters (01.04.2006)
Published in IEEE electron device letters (01.04.2006)
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Journal Article
Performance assessment of scaled strained-Si channel-on-insulator (SSOI) CMOS
Kim, Keunwoo, Chuang, Ching-Te, Rim, Kern, Joshi, Rajiv V.
Published in Solid-state electronics (01.02.2004)
Published in Solid-state electronics (01.02.2004)
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Journal Article
Process/physics-based threshold voltage model for nano-scaled double-gate devices
Kim, Keunwoo, Fossum, Jerry G., Chuang, Ching-Te
Published in International journal of electronics (01.03.2004)
Published in International journal of electronics (01.03.2004)
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Journal Article
Off-state current and performance analysis for double-gate CMOS with non-self-aligned back gate
Keunwoo Kim, Hanafi, H.I., Jin Cai, Ching-Te Chuang
Published in IEEE transactions on electron devices (01.09.2005)
Published in IEEE transactions on electron devices (01.09.2005)
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Journal Article
Floating-body effects in partially depleted SOI CMOS circuits
Pong-Fei Lu, Ching-Te Chuang, Jin Ji, Wagner, L.F., Chang-Ming Hsieh, Kuang, J.B., Hsu, L.L.-C., Pelella, M.M., Chu, S.-F.S., Anderson, C.J.
Published in IEEE journal of solid-state circuits (01.08.1997)
Published in IEEE journal of solid-state circuits (01.08.1997)
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Journal Article
Influence and model of gate oxide breakdown on CMOS inverters
Rodrı́guez, R., Stathis, J.H., Linder, B.P., Joshi, R.V., Chuang, C.T.
Published in Microelectronics and reliability (01.09.2003)
Published in Microelectronics and reliability (01.09.2003)
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Journal Article
Scaling planar silicon devices
Ching-Te Chuang, Bernstein, K., Joshi, R.V., Puri, R., Kim, K., Nowak, E.J., Ludwig, T., Aller, I.
Published in IEEE circuits and devices magazine (01.01.2004)
Published in IEEE circuits and devices magazine (01.01.2004)
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Journal Article
Dynamic body charge modulation for sense amplifiers in partially depleted SOI technology
Kuang, J.B., Allen, D.H., Ching-Te Chuang
Published in IEEE journal of solid-state circuits (01.04.2001)
Published in IEEE journal of solid-state circuits (01.04.2001)
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Journal Article
Compact Modeling Methodology of Strained-Si Channel-on-Insulator (SSOI) MOSFETs
Kim, Keunwoo, Chuang, Ching-Te, Rim, Kern, Cai, Jin, Haensch, Wilfried E.
Published in International journal of electronics (01.05.2004)
Published in International journal of electronics (01.05.2004)
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Journal Article
Back-gate controlled READ SRAM with improved stability
Jae-Joon Kim, Keunwoo Kim, Ching-Te Chuang
Published in 2005 IEEE International SOI Conference Proceedings (2005)
Published in 2005 IEEE International SOI Conference Proceedings (2005)
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Conference Proceeding