Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis
Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Sunter, S., Yung-Fa Chou, Ding-Ming Kwai
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.05.2013)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.05.2013)
Get full text
Journal Article
In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis
YOU, Jhih-Wei, HUANG, Shi-Yu, LIN, Yu-Hsiang, TSAI, Meng-Hsiu, KWAI, Ding-Ming, CHOU, Yung-Fa, WU, Cheng-Wen
Published in IEEE transactions on very large scale integration (VLSI) systems (01.03.2013)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.03.2013)
Get full text
Journal Article
DLL-Assisted Clock Synchronization Method for Multi-Die ICs
Chia-Yuan Cheng, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou
Published in 2017 IEEE International Conference on Computer Design (ICCD) (01.11.2017)
Published in 2017 IEEE International Conference on Computer Design (ICCD) (01.11.2017)
Get full text
Conference Proceeding
3-D Stacked Technology of DRAM-Logic Controller Using Through-Silicon Via (TSV)
Shen, Wen-Wei, Kao, Ming-Jer, Chen, Kuan-Neng, Lin, Yu-Min, Chen, Shang-Chun, Chang, Hsiang-Hung, Chang, Tao-Chih, Lo, Wei-Chung, Lin, Chien-Chung, Chou, Yung-Fa, Kwai, Ding-Ming
Published in IEEE journal of the Electron Devices Society (01.01.2018)
Published in IEEE journal of the Electron Devices Society (01.01.2018)
Get full text
Journal Article
A built-in self-repair scheme for DRAMs with spare rows, columns, and bits
Chih-Sheng Hou, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou
Published in 2016 IEEE International Test Conference (ITC) (01.11.2016)
Published in 2016 IEEE International Test Conference (ITC) (01.11.2016)
Get full text
Conference Proceeding
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs
Yu-Jen Huang, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
Published in 29th VLSI Test Symposium (01.05.2011)
Published in 29th VLSI Test Symposium (01.05.2011)
Get full text
Conference Proceeding
Small delay testing for TSVs in 3-D ICs
Huang, Shi-Yu, Lin, Yu-Hsiang, Tsai, Kun-Han (Hans), Cheng, Wu-Tung, Sunter, Stephen, Chou, Yung-Fa, Kwai, Ding-Ming
Published in DAC Design Automation Conference 2012 (03.06.2012)
Published in DAC Design Automation Conference 2012 (03.06.2012)
Get full text
Conference Proceeding
Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs
Tsung-Fu Hsieh, Jin-Fu Li, Kuan-Te Wu, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou
Published in 2017 International Test Conference in Asia (ITC-Asia) (01.09.2017)
Published in 2017 International Test Conference in Asia (ITC-Asia) (01.09.2017)
Get full text
Conference Proceeding
Performance Characterization of TSV in 3D IC via Sensitivity Analysis
Jhih-Wei You, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
Published in 2010 19th IEEE Asian Test Symposium (01.12.2010)
Published in 2010 19th IEEE Asian Test Symposium (01.12.2010)
Get full text
Conference Proceeding
A Test Method for Finding Boundary Currents of 1T1R Memristor Memories
Tzu-Ying Lin, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou
Published in 2016 IEEE 25th Asian Test Symposium (ATS) (01.11.2016)
Published in 2016 IEEE 25th Asian Test Symposium (ATS) (01.11.2016)
Get full text
Conference Proceeding
BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs
Yun-Chao Yu, Chi-Chun Yang, Jin-Fu Li, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
Published in 2014 IEEE 23rd Asian Test Symposium (01.11.2014)
Published in 2014 IEEE 23rd Asian Test Symposium (01.11.2014)
Get full text
Conference Proceeding
A Test Integration Methodology for 3D Integrated Circuits
Che-Wei Chou, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
Published in 2010 19th IEEE Asian Test Symposium (01.12.2010)
Published in 2010 19th IEEE Asian Test Symposium (01.12.2010)
Get full text
Conference Proceeding
Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs
Kuan-Te Wu, Jin-Fu Li, Yun-Chao Yu, Chih-Sheng Hou, Chi-Chun Yang, Ding-Ming Kwai, Yung-Fa Chou, Chih-Yen Lo
Published in 2014 IEEE 23rd Asian Test Symposium (01.11.2014)
Published in 2014 IEEE 23rd Asian Test Symposium (01.11.2014)
Get full text
Conference Proceeding
A hybrid ECC and redundancy technique for reducing refresh power of DRAMs
Yun-Chao Yu, Chih-Sheng Hou, Li-Jung Chang, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
Published in 2013 IEEE 31st VLSI Test Symposium (VTS) (01.04.2013)
Published in 2013 IEEE 31st VLSI Test Symposium (VTS) (01.04.2013)
Get full text
Conference Proceeding
A built-in self-test scheme for 3D RAMs
Yun-Chao Yu, Che-Wei Chou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
Published in 2012 IEEE International Test Conference (01.11.2012)
Published in 2012 IEEE International Test Conference (01.11.2012)
Get full text
Conference Proceeding