A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application
Mu-Shan Lin, Chien-Chun Tsai, Chih-Hsien Chang, Wen-Hung Huang, Ying-Yu Hsu, Shu-Chun Yang, Chin-Ming Fu, Mao-Hsuan Chou, Tien-Chien Huang, Ching-Fang Chen, Tze-Chiang Huang, Adham, Saman, Min-Jer Wang, Shen, William Wu, Mehta, Ashok
Published in IEEE journal of solid-state circuits (01.04.2014)
Published in IEEE journal of solid-state circuits (01.04.2014)
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Journal Article
A 0.1-3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector
Yao-Chia Liu, Wei-Zen Chen, Mao-Hsuan Chou, Tsung-Hsien Tsai, Yen-Wei Lee, Min-Shueh Yuan
Published in Proceedings of the IEEE 2013 Custom Integrated Circuits Conference (01.09.2013)
Published in Proceedings of the IEEE 2013 Custom Integrated Circuits Conference (01.09.2013)
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Conference Proceeding
An extra low-power 1Tbit/s bandwidth PLL/DLL-less eDRAM PHY using 0.3V low-swing IO for 2.5D CoWoS application
Mu-Shan Lin, Chien-Chun Tsai, Chih-Hsien Chang, Wen-Hung Huang, Ying-Yu Hsu, Shu-Chun Yang, Chin-Ming Fu, Mao-Hsuan Chou, Tien-Chien Huang, Ching-Fang Chen, Tze-Chiang Huang, Adham, Saman, Min-Jer Wang, Shen, William Wu, Mehta, Ashok
Published in 2013 Symposium on VLSI Technology (01.06.2013)
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Published in 2013 Symposium on VLSI Technology (01.06.2013)
Conference Proceeding
Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS
Chou, Mao-Hsuan, Chang, Ya-Tin, Tsai, Tsung-Hsien, Lu, Tsung-Che, Liao, Chia-Chun, Kuo, Hung-Yi, Sheen, Ruey-Bin, Chang, Chih-Hsien, Hsieh, Kenny C. H., Loke, Alvin L. S., Chen, Mark
Published in 2020 IEEE Symposium on VLSI Circuits (01.06.2020)
Published in 2020 IEEE Symposium on VLSI Circuits (01.06.2020)
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Conference Proceeding