A PVT tolerant BPF using turn-off MOSFET for bio applications in 0.13μm CMOS
Kangyeop Choo, Woojae Lee, SeongHwan Cho
Published in 2010 International SoC Design Conference (01.11.2010)
Published in 2010 International SoC Design Conference (01.11.2010)
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Conference Proceeding
A 0.02mm2 fully synthesizable period-jitter sensor using stochastic TDC without reference clock and calibration in 10nm CMOS technology
Kangyeop Choo, Hyunik Kim, Wooseok Kim, Jihyun Kim, Taeik Kim, Hyungjong Ko
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01.02.2018)
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01.02.2018)
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Conference Proceeding
A 0.010mm2 9.92psrms low tracking jitter pixel clock generator with a divider initializer and a nearest phase selector in 28nm CMOS technology
Kangyeop Choo, Sung-Jin Kim, Wooseok Kim, Jihyun Kim, Taeik Kim, Hojin Park
Published in Proceedings of the IEEE 2014 Custom Integrated Circuits Conference (01.09.2014)
Published in Proceedings of the IEEE 2014 Custom Integrated Circuits Conference (01.09.2014)
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Conference Proceeding
Phase locked loop generating adaptive driving voltage and related operating method
Choo, Kangyeop, Jeong, Chanyoung, Kim, Wooseok, Lee, Sunghyuck, Kim, Insung, Kim, Taeik
Year of Publication 11.07.2023
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Year of Publication 11.07.2023
Patent
PHASE LOCKED LOOP GENERATING ADAPTIVE DRIVING VOLTAGE AND RELATED OPERATING METHOD
LEE, SUNGHYUCK, KIM, WOOSEOK, KIM, INSUNG, CHOO, KANGYEOP, KIM, TAEIK, JEONG, CHANYOUNG
Year of Publication 27.10.2022
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Year of Publication 27.10.2022
Patent
PHASE LOCKED LOOP GENERATING ADAPTIVE DRIVING VOLTAGE AND RELATED OPERATING METHOD
KIM, Taeik, JEONG, Chanyoung, CHOO, Kangyeop, KIM, Insung, LEE, Sunghyuck, KIM, Wooseok
Year of Publication 26.10.2022
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Year of Publication 26.10.2022
Patent
Digital phase locked loop circuit adjusting digital gain to maintain loop bandwidth uniformly
Choo, Kangyeop, Kim, Wooseok, Kim, Hyunik, Yu, Wonsik, Kim, Jihyun, Kim, Taeik
Year of Publication 29.01.2019
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Year of Publication 29.01.2019
Patent
DIGITAL PHASE LOCKED LOOP CIRCUIT ADJUSTING DIGITAL GAIN TO MAINTAIN LOOP BANDWIDTH UNIFORMLY
KIM, Jihyun, KIM, Taeik, KIM, Hyunik, CHOO, Kangyeop, YU, Wonsik, KIM, Wooseok
Year of Publication 20.12.2018
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Year of Publication 20.12.2018
Patent
DIGITAL PHASE LOCKED LOOP CIRCUIT ADJUSTING DIGITAL GAIN TO MAINTAIN LOOP BANDWIDTH UNIFORMLY
KIM HYUNIK, YU WONSIK, CHOO KANGYEOP, KIM WOOSEOK, KIM JIHYUN, KIM TAEIK
Year of Publication 04.01.2019
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Year of Publication 04.01.2019
Patent