Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells
Luo, Shien-Chun, Chang, Kuo-Chiang, Chen, Ming-Pin, Huang, Ching-Ji, Chiu, Yi-Fang, Chen, Po-Hsun, Cheng, Liang-Chia, Liu, Chih-Wei, Chu, Yuan-Hua
Published in IEEE transactions on circuits and systems. II, Express briefs (01.12.2014)
Published in IEEE transactions on circuits and systems. II, Express briefs (01.12.2014)
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Journal Article
An ultra-low voltage hearing aid chip using variable-latency design technique
Kuo-Chiang Chang, Shien-Chun Luo, Ching-Ji Huang, Chih-Wei Liu, Yuan-Hua Chu, Shyh-Jye Jou
Published in 2014 IEEE International Symposium on Circuits and Systems (ISCAS) (01.06.2014)
Published in 2014 IEEE International Symposium on Circuits and Systems (ISCAS) (01.06.2014)
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Conference Proceeding
An accurate PLL behavioral model for fast Monte Carlo analysis under process variation
Chin-Cheng Kuo, Meng-Jung Lee, I-Ching Tsai, Liu, C.-N.J., Ching-Ji Huang
Published in 2007 IEEE International Behavioral Modeling and Simulation Workshop (01.09.2007)
Published in 2007 IEEE International Behavioral Modeling and Simulation Workshop (01.09.2007)
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Conference Proceeding
MORAS: An energy-scalable system using adaptive voltage scaling
Chang, Kuo-Chiang, Luo, Shien-Chun, Huang, Ching-Ji, Peng, Jia-Hung, Chu, Yuan-Hua
Published in 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) (01.04.2018)
Published in 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) (01.04.2018)
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Conference Proceeding
A 320-MHz 8bit × 8bit pipelined multiplier in ultra-low supply voltage
Yung-Chih Liang, Ching-Ji Huang, Wei-Bin Yang
Published in 2008 IEEE Asian Solid-State Circuits Conference (01.11.2008)
Published in 2008 IEEE Asian Solid-State Circuits Conference (01.11.2008)
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Conference Proceeding