A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface
Haechang Lee, Kun-Yung Ken Chang, Jung-Hoon Chun, Ting Wu, Frans, Y., Leibowitz, B., Nhat Nguyen, Chin, T.J., Kaviani, K., Shen, J., Xudong Shi, Beyene, W.T., Li, S., Navid, R., Aleksic, M., Lee, F.S., Quan, F., Zerbe, J., Perego, R., Assaderaghi, F.
Published in IEEE journal of solid-state circuits (01.04.2009)
Published in IEEE journal of solid-state circuits (01.04.2009)
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Journal Article
Conference Proceeding
Clocking and circuit design for a parallel I/O on a first-generation CELL processor
Ken Chang, Pamarti, S., Kaviani, K., Alon, E., Xudong Shi, Chin, T.J., Jie Shen, Yip, G., Madden, C., Schmitt, R., Yuan, C., Assaderaghi, F., Horowitz, M.
Published in ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005 (2005)
Published in ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005 (2005)
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Conference Proceeding
Clocking circuits for a 16Gb/s memory interface
Ting Wu, Xudong Shi, Kaviani, K., Haechang Lee, Jung-Hoon Chun, Chin, T.J., Jie Shen, Perego, R., Chang, K.
Published in 2008 IEEE Custom Integrated Circuits Conference (01.09.2008)
Published in 2008 IEEE Custom Integrated Circuits Conference (01.09.2008)
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Conference Proceeding
Low-skew clock distribution using zero-phase-clock-buffer DLLs
Ting Wu, Aryanfar, F., Hae-Chang Lee, Jie Shen, Chin, T.J., Werner, C., Chang, K.
Published in 2010 IEEE International Solid-State Circuits Conference - (ISSCC) (01.02.2010)
Published in 2010 IEEE International Solid-State Circuits Conference - (ISSCC) (01.02.2010)
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Conference Proceeding
A 16Gb/s/link, 64GB/s bidirectional asymmetric memory interface cell
Ken Chang, Haechang Lee, Jung-Hoon Chun, Ting Wu, Chin, T.J., Kaviani, K., Jie Shen, Xudong Shi, Beyene, W., Frans, Y., Leibowitz, B., Nhat Nguyen, Quan, F., Zerbe, J., Perego, R., Assaderaghi, F.
Published in 2008 IEEE Symposium on VLSI Circuits (01.06.2008)
Published in 2008 IEEE Symposium on VLSI Circuits (01.06.2008)
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Conference Proceeding
A 16Gb/s 65nm CMOS transceiver for a memory interface
Jung-Hoon Chun, Haechang Lee, Jie Shen, Chin, T.J., Ting Wu, Xudong Shi, Kaviani, K., Beyene, W., Leibowitz, B., Perego, R., Chang, K.
Published in 2008 IEEE Asian Solid-State Circuits Conference (01.11.2008)
Published in 2008 IEEE Asian Solid-State Circuits Conference (01.11.2008)
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Conference Proceeding