High-Performance Stacked Double-Layer N-Channel Poly-Si Nanosheet Multigate Thin-Film Transistors
Chen, Lun-Chun, Lin, Yu-Ru, Chang, Yu-Shuo, Wu, Yung-Chun
Published in IEEE electron device letters (01.09.2017)
Published in IEEE electron device letters (01.09.2017)
Get full text
Journal Article
A PUF scheme using competing oxide rupture with bit error rate approaching zero
Meng-Yi Wu, Tsao-Hsin Yang, Lun-Chun Chen, Chi-Chang Lin, Hao-Chun Hu, Fang-Ying Su, Chih-Min Wang, Huang, James Po-Hao, Hsin-Ming Chen, Lu, Chris Chun-Hung, Yang, Evans Ching-Sung, Shen, Rick Shih-Jye
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01.02.2018)
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01.02.2018)
Get full text
Conference Proceeding
Low-Voltage Programmable Gate-All-Around (GAA) Nanosheet TFT Nonvolatile Memory Using Band-to-Band Tunneling Induced Hot Electron (BBHE) Method
Chen, Lun-Chun, Chen, Hung-Bin, Chang, Yu-Shuo, Lin, Shih-Han, Han, Ming-Hung, Wu, Jia-Jiun, Yeh, Mu-Shih, Lin, Yu-Ru, Wu, Yung-Chun
Published in IEEE journal of the Electron Devices Society (2019)
Published in IEEE journal of the Electron Devices Society (2019)
Get full text
Journal Article
The physical analysis on electrical junction of junctionless FET
Chen, Lun-Chun, Yeh, Mu-Shih, Lin, Yu-Ru, Lin, Ko-Wei, Wu, Min-Hsin, Thirunavukkarasu, Vasanthan, Wu, Yung-Chun
Published in AIP advances (01.02.2017)
Published in AIP advances (01.02.2017)
Get full text
Journal Article
Junctionless Poly-Si Nanowire FET With Gated Raised S/D
Chen, Lun-Chun, Yeh, Mu-Shih, Lin, Ko-Wei, Wu, Min-Hsin, Wu, Yung-Chun
Published in IEEE journal of the Electron Devices Society (01.03.2016)
Published in IEEE journal of the Electron Devices Society (01.03.2016)
Get full text
Journal Article
A single poly-Si gate-all-around junctionless fin field-effect transistor for use in one-time programming nonvolatile memory
Yeh, Mu-Shih, Wu, Yung-Chun, Liu, Kuan-Cheng, Chung, Ming-Hsien, Jhan, Yi-Ruei, Hung, Min-Feng, Chen, Lun-Chun
Published in Nanoscale research letters (06.11.2014)
Published in Nanoscale research letters (06.11.2014)
Get full text
Journal Article
Impacts of Poly-Si Nanowire Shape on Gate-All-Around Flash Memory With Hybrid Trap Layer
CHEN, Hung-Bin, WU, Yung-Chun, YANG, Chao-Kan, CHEN, Lun-Chun, CHIANG, Ji-Hong, CHANG, Chun-Yen
Published in IEEE electron device letters (01.10.2011)
Published in IEEE electron device letters (01.10.2011)
Get full text
Journal Article
Poly-Si Nanowire Nonvolatile Memory With Nanocrystal Indium-Gallium-Zinc-Oxide Charge-Trapping Layer
CHEN, Lun-Chun, WU, Yung-Chun, LIN, Tien-Chun, HUANG, Jyun-Yang, HUNG, Min-Feng, CHEN, Jiang-Hung, CHANG, Chun-Yen
Published in IEEE electron device letters (01.12.2010)
Published in IEEE electron device letters (01.12.2010)
Get full text
Journal Article
Fabrication and characterization of twin poly-Si thin film transistors EEPROM with a nitride charge trapping layer
Hung, Min-Feng, Wu, Yung-Chun, Chiang, Ji-Hong, Chen, Jiang-Hung, Chen, Lun-Chun
Published in Journal of nanoscience and nanotechnology (01.12.2011)
Published in Journal of nanoscience and nanotechnology (01.12.2011)
Get more information
Journal Article