An Overview of Patterned Metal/Dielectric Surface Bonding: Mechanism, Alignment and Characterization
Di Cioccio, L., Gueguen, P., Taibi, R., Landru, D., Gaudin, G., Chappaz, C., Rieutord, F., de Crecy, F., Radu, I., Chapelon, L. L., Clavelier, L.
Published in Journal of the Electrochemical Society (01.01.2011)
Published in Journal of the Electrochemical Society (01.01.2011)
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RF characterization and modelling of high density Through Silicon Vias for 3D chip stacking
Cadix, L., Bermond, C., Fuchs, C., Farcy, A., Leduc, P., DiCioccio, L., Assous, M., Rousseau, M., Lorut, F., Chapelon, L.L., Flechet, B., Sillon, N., Ancey, P.
Published in Microelectronic engineering (01.03.2010)
Published in Microelectronic engineering (01.03.2010)
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Characterization and integration of a CVD porous SiOCH (k<2.5) with enhanced mechanical properties for 65 nm CMOS interconnects and below
Chapelon, L.L., Arnal, V., Broekaart, M., Gosset, L.G., Vitiello, J., Torres, J.
Published in Microelectronic engineering (01.10.2004)
Published in Microelectronic engineering (01.10.2004)
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UV curing effects on mechanical and electrical performances of a PECVD non-porogen porous SiOC:H films (in k [2.2–2.4] range) for 45 nm node and below
Chapelon, L.L., Vitiello, J., Gonchond, J.P., Barbier, D., Torres, J.
Published in Microelectronic engineering (01.11.2006)
Published in Microelectronic engineering (01.11.2006)
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Measuring the Young’s modulus of ultralow- k materials with the non destructive picosecond ultrasonic method
Chapelon, L.L., Vitiello, J., Neira, D., Torres, J., Royer, J.C., Barbier, D., Naudin, F., Tas, G., Mukundhan, P., Clerico, J.
Published in Microelectronic engineering (01.11.2006)
Published in Microelectronic engineering (01.11.2006)
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Evaluation of a PECVD advanced barrier ( k = 3.7) for 32 nm CMOS technology and below
Chapelon, L.L., Petitprez, E., Brun, P., Farcy, A., Torres, J.
Published in Microelectronic engineering (01.11.2007)
Published in Microelectronic engineering (01.11.2007)
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Dense SiOC cap for damage-less ultra low k integration with direct CMP in C45 architecture and beyond
Chapelon, L.L., Chaabouni, H., Imbert, G., Brun, P., Mellier, M., Hamioud, K., Vilmay, M., Farcy, A., Torres, J.
Published in Microelectronic engineering (01.10.2008)
Published in Microelectronic engineering (01.10.2008)
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3D sequential integration with Si CMOS stacked on 28nm industrial FDSOI with Cu-ULK iBEOL featuring RO and HDR pixel
Mota-Frutuoso, T., Lapras, V., Brunet, L., Basset, L., Lugo, J., Fenouillet-Beranger, C., Vinet, M., Lattard, D., Boulard, F., Exbraya, Y., Boutry, D., Billoint, O., Bosch, D., Maneglia, Y., Peizerat, A., Dumas, S., Sicard, G., Kerdiles, S., Kanyandekwe, J., Sideris, P., Mazzocchi, V., Sarrazin, A., Loup, V., Mauguen, G., Morales, C., Alba, P. Acosta, Balan, V., Perrot, C., Sturm, J., Euvrard, C., Aussenac, F., Janaud, A., Chapon, J-D., Guillermet, M., Guglieri, S., Bailly, F., Toresani, P., Fournel, F., Mouhdach, M., Berthoud, A., Chapelon, L-L., Ribotta, M., Ponthenier, F., Magalhaes, A., Maitrejean, S., Moulin, C., Michailos, J., Arnaud, F., Cathelin, A., Arcamone, J., Andrieu, F., Garros, X., Gaillard, F., Batude, P.
Published in 2023 International Electron Devices Meeting (IEDM) (09.12.2023)
Published in 2023 International Electron Devices Meeting (IEDM) (09.12.2023)
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Sidewall restoration of porous ultra low- k dielectrics for sub-45 nm technology nodes
Chaabouni, H., Chapelon, L.L., Aimadeddine, M., Vitiello, J., Farcy, A., Delsol, R., Brun, P., Fossati, D., Arnal, V., Chevolleau, T., Joubert, O., Torres, J.
Published in Microelectronic engineering (01.11.2007)
Published in Microelectronic engineering (01.11.2007)
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New techniques to characterize properties of advanced dielectric barriers for sub-65 nm technology node
Vitiello, J., Ducote, V., Farcy, A., Gosset, L.G., Le-Friec, Y., Hopstaken, M., Jullian, S., Cordeau, M., Ailhas, C., Chapelon, L.L., Barbier, D., Veillerot, M., Danel, A., Torres, J.
Published in Microelectronic engineering (01.11.2006)
Published in Microelectronic engineering (01.11.2006)
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(Invited) An Overview of Patterned Metal/Dielectric Surface Bonding: Mechanism, Alignment and Characterization
Di Cioccio, Lea, Gueguen, P., Taibi, R., Landru, Didier, Gaudin, G., Chappaz, C., Rieutord, François, De Crecy, F., Radu, Ionut, Chapelon, L., Clavelier, Laurent
Published in ECS transactions (01.01.2010)
Published in ECS transactions (01.01.2010)
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Bias-stress-induced evolution of the dielectric properties of porous-ULK/ copper advanced interconnects
Guedj, C., Portier, X., Mondon, F., Arnal, V., Guillaumond, J.F., Arnaud, L., Barnes, J.P., Jousseaume, V., Roule, A., Maitrejean, S., Chapelon, L.L., Reimbold, G., Torres, J., Passemard, G.
Published in Microelectronic engineering (01.06.2005)
Published in Microelectronic engineering (01.06.2005)
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Assessment and Characterization of Stress Induced by Via-First TSV Technology
PARES, G, DE CRECY, F, MOREAU, S, MAURICE, C, BORBELY, A, MAZUIR, J, CHAPELON, L. L, SILLON, N
Published in Journal of microelectronics and electronic packaging (01.10.2011)
Published in Journal of microelectronics and electronic packaging (01.10.2011)
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Integrated monitoring of ULK dielectrics out-gassing and measurement of pore sealing efficiency by residual gas analysis technique
Delsol, R., Chapelon, L., Chaabouni, H., Broussous, L., Schellenberger, M., Ostrovski, A., Normandon, P.
Published in Microelectronic engineering (01.11.2007)
Published in Microelectronic engineering (01.11.2007)
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Evaluation of ellipsometric porosimetry for in-line characterization of ultra low-κ dielectrics
Licitra, C., Bertin, F., Darnon, M., Chevolleau, T., Guedj, C., Cetre, S., Fontaine, H., Zenasni, A., Chapelon, L. L.
Published in Physica status solidi. C (01.05.2008)
Published in Physica status solidi. C (01.05.2008)
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1.62\mu \mathrm Global Shutter Quantum Dot Image Sensor Optimized for Near and Shortwave Infrared
Steckel, J. S., Josse, E., Pattantyus-Abraham, A. G., Bidaud, M., Mortini, B., Bilgen, H., Arnaud, O., Allegret-Maret, S., Saguin, F., Mazet, L., Lhostis, S., Berger, T., Haxaire, K., Chapelon, L. L., Parmigiani, L., Gouraud, P., Brihoum, M., Bar, P., Guillermet, M., Favreau, S., Duru, R., Fantuz, J., Ricq, S., Ney, D., Hammad, I., Roy, D., Arnaud, A., Vianne, B., Nayak, G., Virollet, N., Farys, V., Malinge, P., Tournier, A., Lalanne, F., Crocherie, A., Galvier, J., Rabary, S., Noblanc, O., Wehbe-Alause, H., Acharya, S., Singh, A., Meitzner, J., Aher, D., Yang, H., Romero, J., Chen, B., Hsu, C., Cheng, K. C., Chang, Y., Sarmiento, M., Grange, C., Mazaleyrat, E., Rochereau, K.
Published in 2021 IEEE International Electron Devices Meeting (IEDM) (11.12.2021)
Published in 2021 IEEE International Electron Devices Meeting (IEDM) (11.12.2021)
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Reliability study of 3D-WLP through silicon via with innovative polymer filling integration
Bouchoucha, M., Chausse, P., Moreau, S., Chapelon, L.-L, Sillon, N., Thomas, O.
Published in 2011 IEEE 61st Electronic Components and Technology Conference (ECTC) (01.05.2011)
Published in 2011 IEEE 61st Electronic Components and Technology Conference (ECTC) (01.05.2011)
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Investigation of stress induced voiding and electromigration phenomena on direct copper bonding interconnects for 3D integration
Taibi, R., Di Cioccio, L., Chappaz, C., Francou, M., Dechamp, J., Larre, P., Moreau, S., Chapelon, L.-L, Fortunier, R.
Published in 2011 International Electron Devices Meeting (01.12.2011)
Published in 2011 International Electron Devices Meeting (01.12.2011)
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