DRC Violation Prediction After Global Route Through Convolutional Neural Network
Hung, Wei-Tse, Chen, Yu-Guang, Lin, Jhen-Gang, Yang, Yun-Wei, Tsai, Cheng-Hong, Chao, Mango Chia-Tso
Published in IEEE transactions on very large scale integration (VLSI) systems (01.09.2023)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.09.2023)
Get full text
Journal Article
CNN-Based Stochastic Regression for IDDQ Outlier Identification
Yen, Chia-Heng, Chen, Chun-Teng, Wen, Cheng-Yen, Chen, Ying-Yen, Lee, Jih-Nung, Kao, Shu-Yi, Wu, Kai-Chiang, Chao, Mango Chia-Tso
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.11.2023)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.11.2023)
Get full text
Journal Article
Methodology of Generating Timing-Slack-Based Cell-Aware Tests
Nien, Yu-Teng, Wu, Kai-Chiang, Lee, Dong-Zhen, Chen, Ying-Yen, Chen, Po-Lin, Chern, Mason, Lee, Jih-Nung, Kao, Shu-Yi, Chao, Mango Chia-Tso
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.11.2022)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.11.2022)
Get full text
Journal Article
Outlier Detection for Analog Tests Using Deep Learning Techniques
Lin, Chin-Kuan, Lu, Cheng-Che, Chang, Shuo-Wen, Chu, Ying-Hua, Wu, Kai-Chiang, Chao, Mango Chia-Tso
Published in 2023 IEEE 41st VLSI Test Symposium (VTS) (24.04.2023)
Published in 2023 IEEE 41st VLSI Test Symposium (VTS) (24.04.2023)
Get full text
Conference Proceeding
Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information
Liu, Ching-Min, Yen, Chia-Heng, Lee, Shu-Wen, Wu, Kai-Chiang, Chao, Mango Chia-Tso
Published in 2023 IEEE International Test Conference (ITC) (07.10.2023)
Published in 2023 IEEE International Test Conference (ITC) (07.10.2023)
Get full text
Conference Proceeding
Transformer and Its Variants for Identifying Good Dice in Bad Neighborhoods
Lu, Cheng-Che, Chang, Chi-Chih, Yen, Chia-Heng, Chang, Shuo-Wen, Chu, Ying-Hua, Wu, Kai-Chiang, Chao, Mango Chia-Tso
Published in 2024 IEEE 42nd VLSI Test Symposium (VTS) (22.04.2024)
Published in 2024 IEEE 42nd VLSI Test Symposium (VTS) (22.04.2024)
Get full text
Conference Proceeding
Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks
Yang, Cheng-Hao, Yen, Chia-Heng, Wang, Ting-Rui, Chen, Chun-Teng, Chern, Mason, Chen, Ying-Yen, Lee, Jih-Nung, Kao, Shu-Yi, Wu, Kai-Chiang, Chao, Mango Chia-Tso
Published in 2021 IEEE 39th VLSI Test Symposium (VTS) (25.04.2021)
Published in 2021 IEEE 39th VLSI Test Symposium (VTS) (25.04.2021)
Get full text
Conference Proceeding
CNN-based Stochastic Regression for IDDQ Outlier Identification
Chen, Chun-Teng, Yen, Chia-Heng, Wen, Cheng-Yen, Yang, Cheng-Hao, Wu, Kai-Chiang, Chern, Mason, Chen, Ying-Yen, Kuo, Chun-Yi, Lee, Jih-Nung, Kao, Shu-Yi, Chao, Mango Chia-Tso
Published in 2020 IEEE 38th VLSI Test Symposium (VTS) (01.04.2020)
Published in 2020 IEEE 38th VLSI Test Symposium (VTS) (01.04.2020)
Get full text
Conference Proceeding
Methodology of Generating Timing-Slack-Based Cell-Aware Tests
Nien, Yu-Teng, Wu, Kai-Chiang, Lee, Dong-Zhen, Chen, Ying-Yen, Chen, Po-Lin, Chern, Mason, Lee, Jih-Nung, Kao, Shu-Yi, Chao, Mango Chia-Tso
Published in 2019 IEEE International Test Conference (ITC) (01.11.2019)
Published in 2019 IEEE International Test Conference (ITC) (01.11.2019)
Get full text
Conference Proceeding
Fast WAT test structure for measuring Vt variance based on latch-based comparators
Kao-Chi Lee, Kai-Chiang Wu, Chih-Ying Tsai, Chao, Mango Chia-Tso
Published in 2017 IEEE 35th VLSI Test Symposium (VTS) (01.04.2017)
Published in 2017 IEEE 35th VLSI Test Symposium (VTS) (01.04.2017)
Get full text
Conference Proceeding
Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs
Wang, Yu-Zhe, Wu, Jingjie, Chen, Shi-Hao, Chao, Mango Chia-Tso, Yang, Chia-Hsiang
Published in 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) (01.04.2019)
Published in 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) (01.04.2019)
Get full text
Conference Proceeding
Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks
Yen, Chia-Heng, Wang, Ting-Rui, Liu, Ching-Min, Yang, Cheng-Hao, Chen, Chun-Teng, Chen, Ying-Yen, Lee, Jih-Nung, Kao, Shu-Yi, Wu, Kai-Chiang, Chao, Mango Chia-Tso
Published in IEEE transactions on semiconductor manufacturing (01.08.2024)
Published in IEEE transactions on semiconductor manufacturing (01.08.2024)
Get full text
Journal Article
A clustering- and probability-based approach for time-multiplexed FPGA partitioning
Wu, Guang-Ming, Chao, Mango Chia-Tso, Chang, Yao-Wen
Published in Integration (Amsterdam) (01.12.2004)
Published in Integration (Amsterdam) (01.12.2004)
Get full text
Journal Article
A clustering- and probability-based approach for time-multiplexed FPGA partitioning
Chao, M.C.-T., Guang-Ming Wu, Jiang, I.-H.-R., Yao-Wen Chang
Published in 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) (1999)
Published in 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) (1999)
Get full text
Conference Proceeding
Journal Article
A clustering- and probability-based approach for time-multiplexed FPGA partitioning
Chao, Mango Chia-Tso, Wu, Guang-Ming, Jiang, Iris Hui-Ru, Chang, Yao-Wen
Published in Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design (07.11.1999)
Published in Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design (07.11.1999)
Get full text
Conference Proceeding