Modulation of the effective work function of fully-silicided (FUSI) gate stacks
Kittl, J.A., Lauwers, A., Pawlak, M.A., Veloso, A., Yu, H.Y., Chang, S.Z., Hoffmann, T., Pourtois, G., Brus, S., Demeurisse, C., Vrancken, C., Absil, P.P., Biesemans, S.
Published in Microelectronic engineering (01.09.2007)
Published in Microelectronic engineering (01.09.2007)
Get full text
Journal Article
Conference Proceeding
The Application of an Ultrathin ALD HfSiON Cap Layer on SiON Dielectrics for Ni-FUSI CMOS Technology Targeting at Low-Power Applications
Chang, S.Z., Yu, H.Y., Veloso, A., Lauwers, A., Delabie, A., Everaert, J-L., Kerner, C., Absil, P., Hoffmann, T., Biesemans, S.
Published in IEEE electron device letters (01.07.2007)
Published in IEEE electron device letters (01.07.2007)
Get full text
Journal Article
Electrical Properties of Low- V Metal-Gated n-MOSFETs Using \hbox\hbox/\hbox as Interfacial Layer Between HfLaO High- \kappa Dielectrics and Si Channel
Chang, S.Z., Yu, H.Y., Adelmann, C., Delabie, A., Wang, X.P., Van Elshocht, S., Akheyar, A., Nyns, L., Swerts, J., Aoulaiche, M., Kerner, C., Absil, P., Hoffmann, T.Y., Biesemans, S.
Published in IEEE electron device letters (01.05.2008)
Published in IEEE electron device letters (01.05.2008)
Get full text
Journal Article
Demonstration of Low Vt Ni-FUSI N-MOSFETs With SiON Dielectrics by Using a Dy2O3 Cap Layer
Yu, H.Y, Chang, S.Z, Veloso, A, Lauwers, A, Adelmann, C, Onsia, B, Lehnen, P, Kauerauf, T, Brus, S, Yin, K.M, Absil, P, Biesemans, S
Published in IEEE electron device letters (01.11.2007)
Published in IEEE electron device letters (01.11.2007)
Get full text
Journal Article
Demonstration of Low V Ni-FUSI N-MOSFETs With SiON Dielectrics by Using a \hbox\hbox Cap Layer
Yu, H.Y., Chang, S.Z., Veloso, A., Lauwers, A., Adelmann, C., Onsia, B., Lehnen, P., Kauerauf, T., Brus, S., Yin, K.M., Absil, P., Biesemans, S.
Published in IEEE electron device letters (01.11.2007)
Published in IEEE electron device letters (01.11.2007)
Get full text
Journal Article
Electrical Properties of Low-[Formula Omitted] Metal-Gated n-MOSFETs Using [Formula Omitted] as Interfacial Layer Between HfLaO High-[Formula Omitted] Dielectrics and Si Channel
Chang, S.Z, Yu, H.Y, Adelmann, C, Delabie, A, Wang, X.P, Van Elshocht, S, Akheyar, A, Nyns, L, Swerts, J, Aoulaiche, M, Kerner, C, Absil, P, Hoffmann, T.Y, Biesemans, S
Published in IEEE electron device letters (01.05.2008)
Published in IEEE electron device letters (01.05.2008)
Get full text
Journal Article
Demonstration of low Vt Ni-FUSI N-MOSFETs with SiON dielectrics by using a Dy2O3 cap layer
YU, H. Y, CHANG, S. Z, ABSIL, P, BIESEMANS, S, VELOSO, A, LAUWERS, A, ADELMANN, C, ONSIA, B, LEHNEN, P, KAUERAUF, T, BRUS, S, YIN, K. M
Published in IEEE electron device letters (2007)
Published in IEEE electron device letters (2007)
Get full text
Journal Article
Achieving Low- V Ni-FUSI CMOS by Ultra-Thin \hbox\hbox Capping of Hafnium Silicate Dielectrics
Veloso, A., Yu, H.Y., Chang, S.Z., Adelmann, C., Onsia, B., Brus, S., Demand, M., Lauwers, A., O'Sullivan, B.J., Singanamalla, R., Pourtois, G., Lehnen, P., Van Elshocht, S., De Meyer, K., Jurczak, M., Absil, P.P., Biesemans, S.
Published in IEEE electron device letters (01.11.2007)
Published in IEEE electron device letters (01.11.2007)
Get full text
Journal Article
Achieving Low-[Formula Omitted] Ni-FUSI CMOS by Ultra-Thin [Formula Omitted] Capping of Hafnium Silicate Dielectrics
Veloso, A, Yu, H.Y, Chang, S.Z, Adelmann, C, Onsia, B, Brus, S, Demand, M, Lauwers, A, O'Sullivan, B.J, Singanamalla, R, Pourtois, G, Lehnen, P, Van Elshocht, S, De Meyer, K, Jurczak, M, Absil, P.P, Biesemans, S
Published in IEEE electron device letters (01.11.2007)
Published in IEEE electron device letters (01.11.2007)
Get full text
Journal Article
Demonstration of Metal-Gated Low V n-MOSFETs Using a Poly- \hbox\hbox/\hbox Gate Stack With a Scaled EOT Value
H.Y. Yu, Singanamalla, R., Ragnarsson, L.-A., V.S. Chang, H.-J. Cho, Mitsuhashi, R., Adelmann, C., Van Elshocht, S., Lehnen, P., S.Z. Chang, K.M. Yin, Schram, T., Kubicek, S., De Gendt, S., Absil, P., De Meyer, K., Biesemans, S.
Published in IEEE electron device letters (01.07.2007)
Published in IEEE electron device letters (01.07.2007)
Get full text
Journal Article
Demonstration of metal-gated low Vt n-MOSFETs using a poly -Si /TaN/Dy2O3/SiON gate stack with a scaled EOT value
YU, H. Y, SINGANAMALLA, R, YIN, K. M, SCHRAM, T, KUBICEK, S, DE GENDT, S, ABSIL, P, DE MEYER, K, BIESEMANS, S, RAGNARSSON, L.-A, CHANG, V. S, CHO, H.-J, MITSUHASHI, R, ADELMANN, C, VAN ELSHOCHT, S, LEHNEN, P, CHANG, S. Z
Published in IEEE electron device letters (01.07.2007)
Published in IEEE electron device letters (01.07.2007)
Get full text
Journal Article
Achieving low-VT Ni-FUSI CMOS via lanthanide incorporation in the gate stack
Veloso, A., Yu, H.Y., Lauwers, A., Chang, S.Z., Adelmann, C., Onsia, B., Demand, M., Brus, S., Vrancken, C., Singanamalla, R., Lehnen, P., Kittl, J., Kauerauf, T., Vos, R., O′Sullivan, B.J., Van Elshocht, S., Mitsuhashi, R., Whittemore, G., Yin, K.M., Niwa, M., Hoffmann, T., Absil, P., Jurczak, M., Biesemans, S.
Published in Solid-state electronics (01.09.2008)
Published in Solid-state electronics (01.09.2008)
Get full text
Journal Article
Conference Proceeding
Low Vt Ni-FUSI CMOS Technology using a DyO cap layer with either single or dual Ni-phases
Yu, H.Y., Chang, S.Z., Veloso, A., Lauwers, A., Adelmann, C., Onsia, B., Van Elshocht, S., Singanamalla, R., Demand, M., Vos, R., Kauerauf, T., Brus, S., Shi, X., Kubicek, S., Vrancken, C., Mitsuhashi, R., Lehnen, P., Kittl, J., Niwa, M., Yin, K.M., Hoffmann, T., Degendt, S., Jurczak, M., Absil, P., Biesemans, S.
Published in 2007 IEEE Symposium on VLSI Technology (01.06.2007)
Published in 2007 IEEE Symposium on VLSI Technology (01.06.2007)
Get full text
Conference Proceeding
Low VT metal-gate/high-k nMOSFETs - PBTI dependence and VT Tune-ability on La/Dy-capping layer locations and Laser annealing conditions
Chang, S.Z., Hoffmann, T.Y., Yu, H.Y., Aoulaiche, M., Rohr, E., Adelmann, C., Kaczer, B., Delabie, A., Favia, P., Van Elshocht, S., Kubicek, S., Scharm, T., Witters, T., Ragnarsson, L.A., Wang, X.P., Cho, H.J., Mueller, M., Chiarella, T., Absil, P., Biesemans, S.
Published in 2008 Symposium on VLSI Technology (01.06.2008)
Published in 2008 Symposium on VLSI Technology (01.06.2008)
Get full text
Conference Proceeding
Achieving low VT Ni-FUSI CMOS via lanthanide incorporation in the gate stack
Veloso, A., Yu, H.Y., Lauwers, A., Chang, S.Z., Adelmann, C., Onsia, B., Demand, M., Brus, S., Vrancken, C., Singanamalla, R., Lehnen, P., Kittl, J., Kauerauf, T., Vos, R., O'Sullivan, B.J., Van Elshocht, S., Mitsuhashi, R., Whittemore, G., Yin, K.M., Niwa, M., Hoffmann, T., Absil, P., Jurczak, M., Biesemans, S.
Published in ESSDERC 2007 - 37th European Solid State Device Research Conference (01.09.2007)
Published in ESSDERC 2007 - 37th European Solid State Device Research Conference (01.09.2007)
Get full text
Conference Proceeding
The taste compounds in commercial Toha-jeot
Lee, E.H, Lee, J.S, Joo, D.S, Park, J.J, Kim, H.K. (Pusan National Fisheries University, Pusan (Korea Republic). Department of Food Science and Technology), Chang, S.Z. (Pusan National Fisheries University, Pusan (Korea Republic). Graduate School of Industry)
Published in Hangug ṅyeṅṅyaṅ sigryaṅ haghoi ji (01.04.1996)
Get more information
Published in Hangug ṅyeṅṅyaṅ sigryaṅ haghoi ji (01.04.1996)
Journal Article
Integrate LaOx-capping layer into metal gated CMOS devices using a gate-first approach for sub-45nm technology node and the device reliability thereof
HongYu Yu, Chang, S.Z., Kubicek, S., Schram, T., Wang, X.P., Biesemans, S.
Published in 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (01.10.2008)
Published in 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (01.10.2008)
Get full text
Conference Proceeding
A 90-nm CMOS device technology with high-speed, general-purpose, and low-leakage transistors for system on chip applications
Wu, C.C., Leung, Y.K., Chang, C.S., Tsai, M.H., Huang, H.T., Lin, D.W., Sheu, Y.M., Hsieh, C.H., Liang, W.J., Han, L.K., Chen, W.M., Chang, S.Z., Wu, S.Y., Lin, S.S., Lin, H.C., Wang, C.H., Wang, P.W., Lee, T.L., Fu, C.Y., Chang, C.W., Chen, S.C., Jang, S.M., Shue, S.L., Lin, H.T., See, Y.C., Mii, Y.J., Diaz, C.H., Lin, B.J., Liang, M.S., Sun, Y.C.
Published in Digest. International Electron Devices Meeting (2002)
Published in Digest. International Electron Devices Meeting (2002)
Get full text
Conference Proceeding
High-k/ metal-gate stack work-function tuning by rare-earth capping layers: Interface dipole or bulk charge?
Yu, H.Y., Chang, S.Z., Aoulaiche, M., Kaczer, B., Absil, P., Adelmann, C., Hoffmann, T., Biesemans, S., Wann, C., Mii, Y.J.
Published in 2009 International Symposium on VLSI Technology, Systems, and Applications (01.04.2009)
Published in 2009 International Symposium on VLSI Technology, Systems, and Applications (01.04.2009)
Get full text
Conference Proceeding
Study of asymmetric broadening of Raman scattering in In/sub x/Ga/sub 1-x/As/InP and In/sub x/Ga/sub 1-x/As/GaAs epilayers
Shen, J.L., Chang, S.Z., Lee, S.C., Chen, Y.F.
Published in Proceedings of 1994 IEEE 6th International Conference on Indium Phosphide and Related Materials (IPRM) (1994)
Published in Proceedings of 1994 IEEE 6th International Conference on Indium Phosphide and Related Materials (IPRM) (1994)
Get full text
Conference Proceeding