A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs
Chang, K.-Y.K., Wei, J., Huang, C., Li, S., Donnelly, K., Horowitz, M., Yingxuan Li, Sidiropoulos, S.
Published in IEEE journal of solid-state circuits (01.05.2003)
Published in IEEE journal of solid-state circuits (01.05.2003)
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