Efficient FPGA based architecture for high‐order FIR filtering using simultaneous DSP and LUT reduced utilization
Maamoun, Mountassar, Hassani, Adnane, Dahmani, Samir, Ait Saadi, Hocine, Zerari, Ghania, Chabini, Noureddine, Beguenane, Rachid
Published in IET circuits, devices & systems (01.08.2021)
Published in IET circuits, devices & systems (01.08.2021)
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Journal Article
Efficient Realization of BCD Multipliers Using FPGAs
Chabini, Noureddine, Langlois, J. M. Pierre, al-Khalili, Dhamin, Gao, Shuli
Published in International Journal of Reconfigurable Computing (01.01.2017)
Published in International Journal of Reconfigurable Computing (01.01.2017)
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Journal Article
Ultra-fast and efficient implementation schemes of complex matrix multiplication algorithm for VLIW architectures
Najoui, Mohamed, Bahtat, Mounir, Klilou, Abdessamad, Hatim, Anas, Belkouch, Said, Jbari, Atman, Chabini, Noureddine
Published in Computers & electrical engineering (01.09.2022)
Published in Computers & electrical engineering (01.09.2022)
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Journal Article
FPGA-Based 8x8 Bits Signed Multipliers Using LUTs
Chabini, Noureddine, Beguenane, Rachid
Published in 2023 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE) (24.09.2023)
Published in 2023 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE) (24.09.2023)
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Conference Proceeding
FPGA-Based Digital FIR Filters With Small Coefficients and Large Data Input
Chabini, Noureddine, Beguenane, Rachid
Published in 2023 IEEE 13th Annual Computing and Communication Workshop and Conference (CCWC) (08.03.2023)
Published in 2023 IEEE 13th Annual Computing and Communication Workshop and Conference (CCWC) (08.03.2023)
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Conference Proceeding
FPGA-Based Designs of the Factorial Function
Chabini, Noureddine, Beguenane, Rachid
Published in 2022 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE) (18.09.2022)
Published in 2022 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE) (18.09.2022)
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Conference Proceeding
Frequency Optimized FPGA-Based Digital FIR Filters with Data Inputs and Coefficients of Large Size
Chabini, Noureddine, Aaroud, Abdessadek
Published in 2021 IEEE 12th Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON) (27.10.2021)
Published in 2021 IEEE 12th Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON) (27.10.2021)
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Conference Proceeding
An Algorithm for Gate Resizing to Reduce Power Dissipation in Combinational Digital Designs
Chabini, Noureddine, Belkouch, Said, Najoui, Mohamed
Published in 2022 IEEE 3rd International Conference on Electronics, Control, Optimization and Computer Science (ICECOCS) (01.12.2022)
Published in 2022 IEEE 3rd International Conference on Electronics, Control, Optimization and Computer Science (ICECOCS) (01.12.2022)
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Conference Proceeding
Path Balancing for Reducing Dynamic Power Consumption in Digital Designs Containing IP-Blocks
Chabini, Noureddine, Wolf, Marilyn C.
Published in 2023 IEEE World AI IoT Congress (AIIoT) (07.06.2023)
Published in 2023 IEEE World AI IoT Congress (AIIoT) (07.06.2023)
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Conference Proceeding