Cryogenic MOSFET Subthreshold Current: From Resistive Networks to Percolation Transport in 1-D Systems
Catapano, E., Casse, M., Ghibaudo, G.
Published in IEEE transactions on electron devices (01.08.2023)
Published in IEEE transactions on electron devices (01.08.2023)
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Journal Article
On the Zero Temperature Coefficient in Cryogenic FD-SOI MOSFETs
Catapano, E., Frutuoso, T. Mota, Casse, M., Ghibaudo, G.
Published in IEEE transactions on electron devices (01.03.2023)
Published in IEEE transactions on electron devices (01.03.2023)
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Journal Article
Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm
Barraud, S., Berthome, M., Coquand, R., Casse, M., Ernst, T., Samson, M., Perreau, P., Bourdelle, K. K., Faynot, O., Poiroux, T.
Published in IEEE electron device letters (01.09.2012)
Published in IEEE electron device letters (01.09.2012)
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Journal Article
Modeling of 1D confinement in FD-SOI trigate nanowires at deep cryogenic temperatures
Catapano, E., Cassé, M., Gaillard, F., Meunier, T., Vinet, M., Ghibaudo, G.
Published in Solid-state electronics (01.12.2022)
Published in Solid-state electronics (01.12.2022)
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Journal Article
TCAD simulations of FDSOI devices down to deep cryogenic temperature
Catapano, E., Cassé, M., Gaillard, F., de Franceschi, S., Meunier, T., Vinet, M., Ghibaudo, G.
Published in Solid-state electronics (01.08.2022)
Published in Solid-state electronics (01.08.2022)
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Journal Article
Modelling of self-heating effect in FDSOI and bulk MOSFETs operated in deep cryogenic conditions
Ghibaudo, G., Cassé, M., di Santa Maria, F. Serra, Theodorou, C., Balestra, F.
Published in Solid-state electronics (01.06.2022)
Published in Solid-state electronics (01.06.2022)
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Journal Article
Modeling and simulations of FDSOI five-gate qubit MOS devices down to deep cryogenic temperatures
Catapano, E., Aprà, A., Cassé, M., Gaillard, F., de Franceschi, S., Meunier, T., Vinet, M., Ghibaudo, G.
Published in Solid-state electronics (01.07.2022)
Published in Solid-state electronics (01.07.2022)
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Journal Article
Comprehensive Kubo-Greenwood modelling of FDSOI MOS devices down to deep cryogenic temperatures
Serra di Santa Maria, F., Contamin, L., Cassé, M., Theodorou, C., Balestra, F., Ghibaudo, G.
Published in Solid-state electronics (01.06.2022)
Published in Solid-state electronics (01.06.2022)
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Journal Article
Prehospital transfusion of labile blood product using intraosseous perfusion with multi‐lumen extender: Why not?
Aloird, J., Bernard, P., Javaudin, O., Casse, M., Richez, M., Hitier, J.‐B., Sarda, A., Colleu, F., Boissier, J., Freiermuth, J.‐P.
Published in Transfusion (Philadelphia, Pa.) (25.07.2024)
Published in Transfusion (Philadelphia, Pa.) (25.07.2024)
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Journal Article
Performance of Omega-Shaped-Gate Silicon Nanowire MOSFET With Diameter Down to 8 nm
Barraud, S., Coquand, R., Casse, M., Koyama, M., Hartmann, J.-M, Maffini-Alvaro, V., Comboroure, C., Vizioz, C., Aussenac, F., Faynot, O., Poiroux, T.
Published in IEEE electron device letters (01.11.2012)
Published in IEEE electron device letters (01.11.2012)
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Journal Article
Underestimation of measured self‐heating in nanowires by using gate resistance technique
Mariniello, G., Cassé, M., Reimbold, G., Pavanello, M.A.
Published in Electronics letters (10.11.2016)
Published in Electronics letters (10.11.2016)
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Journal Article
New constraints on the primordial black hole number density from Galactic γ-ray astronomy
Lehoucq, R., Cassé, M., Casandjian, J.-M., Grenier, I.
Published in Astronomy and astrophysics (Berlin) (01.07.2009)
Published in Astronomy and astrophysics (Berlin) (01.07.2009)
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Journal Article
A Review of Low Temperature Process Modules Leading Up to the First (≤500 °C) Planar FDSOI CMOS Devices for 3-D Sequential Integration
Fenouillet-Beranger, C., Brunet, L., Batude, P., Brevard, L., Garros, X., Casse, M., Lacord, J., Sklenard, B., Acosta-Alba, P., Kerdiles, S., Tavernier, A., Vizioz, C., Besson, P., Gassilloud, R., Pedini, J.-M., Kanyandekwe, J., Mazen, F., Magalhaes-Lucas, A., Cavalcante, C., Bosch, D., Ribotta, M., Lapras, V., Vinet, M., Andrieu, F., Arcamone, J.
Published in IEEE transactions on electron devices (01.07.2021)
Published in IEEE transactions on electron devices (01.07.2021)
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Journal Article
Experimental Demonstration of Ω-Gate SOI Nanowire MOS Transistors' Mobility Variation Induced by Substrate Bias
Bergamaschi, F. E., Ribeiro, T. A., Paz, B. C., de Souza, M., Barraud, S., Casse, M., Vinet, M., Faynot, O., Pavanello, M. A.
Published in IEEE transactions on electron devices (01.07.2022)
Published in IEEE transactions on electron devices (01.07.2022)
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Journal Article
Cryogenic Operation of Thin-Film FDSOI nMOS Transistors: The Effect of Back Bias on Drain Current and Transconductance
Casse, M., Paz, B. Cardoso, Ghibaudo, G., Poiroux, T., Barraud, S., Vinet, M., de Franceschi, S., Meunier, T., Gaillard, F.
Published in IEEE transactions on electron devices (01.11.2020)
Published in IEEE transactions on electron devices (01.11.2020)
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Journal Article
Sedimentary Records in the Lesser Antilles Fore‐Arc Basins Provide Evidence of Large Late Quaternary Megathrust Earthquakes
Seibert, C., Feuillet, N., Ratzov, G., Beck, C., Morena, P., Johannes, L., Ducassou, E., Cattaneo, A., Goldfinger, C., Moreno, E., Bieber, A., Bénâtre, G., Caron, B., Caron, M., Casse, M., Cavailhes, T., Del Manzo, G., Deschamps, C. E., Desiage, P. A., Duboc, Q., Fauquembergue, K., Ferrant, A., Guyard, H., Jacques, E., Laurencin, M., Leclerc, F., Patton, J., Saurel, J. M., St‐Onge, G., Woerther, P.
Published in Geochemistry, geophysics, geosystems : G3 (01.02.2024)
Published in Geochemistry, geophysics, geosystems : G3 (01.02.2024)
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Journal Article
Drain current model for short-channel triple gate junctionless nanowire transistors
Paz, B.C., Cassé, M., Barraud, S., Reimbold, G., Faynot, O., Ávila-Herrera, F., Cerdeira, A., Pavanello, M.A.
Published in Microelectronics and reliability (01.08.2016)
Published in Microelectronics and reliability (01.08.2016)
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Journal Article
FDSOI devices with thin BOX and ground plane integration for 32 nm node and below
Fenouillet-Beranger, C., Denorme, S., Perreau, P., Buj, C., Faynot, O., Andrieu, F., Tosti, L., Barnola, S., Salvetat, T., Garros, X., Cassé, M., Allain, F., Loubet, N., Pham-Nguyen, L., Deloffre, E., Gros-Jean, M., Beneyton, R., Laviron, C., Marin, M., Leyris, C., Haendler, S., Leverd, F., Gouraud, P., Scheiblin, P., Clement, L., Pantel, R., Deleonibus, S., Skotnicki, T.
Published in Solid-state electronics (01.07.2009)
Published in Solid-state electronics (01.07.2009)
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Journal Article
Conference Proceeding
Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K
Paz, B.C., Doria, R.T., Cassé, M., Barraud, S., Reimbold, G., Vinet, M., Faynot, O., Pavanello, M.A.
Published in Microelectronics and reliability (01.12.2017)
Published in Microelectronics and reliability (01.12.2017)
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Journal Article
Variability Evaluation of 28nm FD-SOI Technology at Cryogenic Temperatures down to 100mK for Quantum Computing
Paz, B. Cardoso, Le Guevel, L., Casse, M., Billiot, G., Pillonnet, G., Jansen, A. G. M., Maurand, R., Haendler, S., Juge, A., Vincent, E., Galy, P., Ghibaudo, G., Vinet, M., de Franceschi, S., Meunier, T., Gaillard, F.
Published in 2020 IEEE Symposium on VLSI Technology (01.06.2020)
Published in 2020 IEEE Symposium on VLSI Technology (01.06.2020)
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Conference Proceeding