Search Results - "CURELLO GUISEPPE" :: K.UTB vyhledávací portál

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Verfahren zur Erzeugung eines Halbleitersubstrats mit vergrabener Dotierung

by FAUL, JUERGEN, CURELLO, GUISEPPE
Year of Publication 05.08.2004

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Method for setting the threshold voltage of a MOS transistor

by Wurzer, Helmut, Curello, Guiseppe
Year of Publication 17.09.2002

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Method for setting the threshold voltage of a MOS transistor

by WURZER HELMUT, CURELLO GUISEPPE
Year of Publication 17.09.2002

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Method to adjust the threshold-voltage of a MOS-transistor

by WURZER, HELMUT, CURELLO, GUISEPPE
Year of Publication 01.09.2002

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Method for manufacturing a field effect transistor

by Curello, Guiseppe, Kieslich, Albrecht
Year of Publication 04.04.2002

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Method for manufacturing a field effect transistor

by KIESLICH ALBRECHT, CURELLO GUISEPPE
Year of Publication 04.04.2002

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Verfahren zur Einstellung der Schwellenspannung eines MOS-Transistors

by WURZER, HELMUT, CURELLO, GUISEPPE
Year of Publication 24.01.2002

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Adjusting threshold voltage of MOS transistor having a polycrystalline silicon gate comprises implanting germanium ions into gate to change electron affinity of gate

by WURZER, HELMUT, CURELLO, GUISEPPE
Year of Publication 04.10.2001

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Method for setting the threshold voltage of a MOS transistor

by Curello, Guiseppe, Wurzer, Helmut
Year of Publication 20.09.2001

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Method for setting the threshold voltage of a MOS transistor

by WURZER HELMUT, CURELLO GUISEPPE
Year of Publication 20.09.2001

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Selective spacer formation on transistors of different classes on the same device

by BOHR MARK, CURELLO GUISEPPE
Year of Publication 10.06.2009

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Selektives Bilden von Abstandhaltern auf Transistoren unterschiedlicher Klassen auf derselben Baugruppe

by JAN, CHIA-HONG, POST, IAN R, BOHR, MARK, CURELLO, GUISEPPE
Year of Publication 20.05.2009

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DEVICE WITH STEPPED SOURCE/DRAIN REGI0N PROFILE

by TYAGI SUNIT, SELL BERNHARD, CURELLO GUISEPPE, AUTH CHRIS
Year of Publication 31.08.2007

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DEVICE WITH STEPPED SOURCE/DRAIN REGION PROFILE

by TYAGI, SUNIT, AUTH, CHRIS, CURELLO, GUISEPPE, SELL, BERNHARD
Year of Publication 13.07.2006

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Selektives Bilden von Abstandhaltern auf Transistoren unterschiedlicher Klassen auf derselben Baugruppe

by JAN, CHIA-HONG, POST, IAN R, BOHR, MARK, CURELLO, GUISEPPE
Year of Publication 28.03.2013

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Selective spacer formation on transistors of different classes on the same device

by BOHR MARK, JAN CHIA-HONG, CURELLO GUISEPPE, POST IAN R
Year of Publication 04.07.2012

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Sacrificial capping layer for transistor performance enhancement

by LEE SEOK-HEE, TYAGI SUNIT, NAGISETTY RAMUNE, CURELLO GUISEPPE, NATARAJAN SANJAY
Year of Publication 04.01.2007

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Verfahren zur Erzeugung eines dotierten Halbleitersubstrats

by FAUL, JUERGEN, CURELLO, GUISEPPE
Year of Publication 31.01.2002

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Device with stepped source/drain region profile

by TYAGI SUNIT, SELL BERNHARD, CURELLO GUISEPPE, AUTH CHRIS
Year of Publication 08.06.2011

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Transistor-Bauteil mit gestuftem Profil im Quellen/Senken-Bereich sowie Verfahren zur Herstellung desselben

by TYAGI, SUNIT, AUTH, CHRIS, CURELLO, GUISEPPE, SELL, BERNHARD
Year of Publication 15.04.2010

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