Mechanism to enter or exit retention level voltage while a system-on-a-chip is in low power mode
Crews, Darren S, Lu, Chin Seng, Bibikar, Vasudev, Ramachandran, Aswin, Rajesh, Moorthy
Year of Publication 25.08.2020
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Year of Publication 25.08.2020
Patent
MECHANISM TO ENTER OR EXIT RETENTION LEVEL VOLTAGE WHILE A SYSTEM-ON-A-CHIP IS IN LOW POWER MODE
Crews, Darren S, Lu, Chin Seng, Bibikar, Vasudev, Ramachandran, Aswin, Rajesh, Moorthy
Year of Publication 04.04.2019
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Year of Publication 04.04.2019
Patent
LOW POWER KEY PHRASE DETECTION
Ratnayake, Senaka Cuda Bandara, Crews, Darren S, Elias, Vinu K, Durley, Paul S, Rajesh, Moorthy
Year of Publication 09.08.2018
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Year of Publication 09.08.2018
Patent
SYSTEM AND METHOD FOR DATA TRANSMISSION AND POWER SUPPLY CAPABILITY OVER AN AUDIO JACK FOR MOBILE DEVICES
MILLETT, Howard, D, VOGEL, Brian, K, VEMPRALA, Sai, Hemachandra, NEGI, Indira, ESSAIAN, Alexander, CREWS, Darren, S, YANG, Xiaochao, SAMPLE, Alanson, P, KRISHNAMURTHY, Lakshman
Year of Publication 17.04.2019
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Year of Publication 17.04.2019
Patent