A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth
Youngdon Choi, Ickhyun Song, Mu-Hui Park, Hoeju Chung, Sanghoan Chang, Beakhyoung Cho, Jinyoung Kim, Younghoon Oh, Duckmin Kwon, Jung Sunwoo, Junho Shin, Yoohwan Rho, Changsoo Lee, Min Gu Kang, Jaeyun Lee, Yongjin Kwon, Soehee Kim, Jaehwan Kim, Yong-Jun Lee, Qi Wang, Sooho Cha, Sujin Ahn, Horii, Hideki, Jaewook Lee, Kisung Kim, Hansung Joo, Kwangjin Lee, Yeong-Taek Lee, Jeihwan Yoo, Jeong, G.
Published in 2012 IEEE International Solid-State Circuits Conference (01.02.2012)
Published in 2012 IEEE International Solid-State Circuits Conference (01.02.2012)
Get full text
Conference Proceeding
A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation
Oh, Tae-Young, Chung, Hoeju, Park, Jun-Young, Lee, Ki-Won, Oh, Seunghoon, Doo, Su-Yeon, Kim, Hyoung-Joo, Lee, ChangYong, Kim, Hye-Ran, Lee, Jong-Ho, Lee, Jin-Il, Ha, Kyung-Soo, Choi, YoungRyeol, Cho, Young-Chul, Bae, Yong-Cheol, Jang, Taeseong, Park, Chulsung, Park, Kwangil, Jang, SeongJin, Choi, Joo Sun
Published in IEEE journal of solid-state circuits (01.01.2015)
Published in IEEE journal of solid-state circuits (01.01.2015)
Get full text
Journal Article
A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW
Hoeju Chung, Byung Hoon Jeong, ByungJun Min, Youngdon Choi, Beak-Hyung Cho, Junho Shin, Jinyoung Kim, Jung Sunwoo, Joon-min Park, Qi Wang, Yong-jun Lee, Sooho Cha, Dukmin Kwon, Sangtae Kim, Sunghoon Kim, Yoohwan Rho, Mu-Hui Park, Jaewhan Kim, Ickhyun Song, Sunghyun Jun, Jaewook Lee, KiSeung Kim, Ki-won Lim, Won-ryul Chung, ChangHan Choi, HoGeun Cho, Inchul Shin, Woochul Jun, Seokwon Hwang, Ki-Whan Song, KwangJin Lee, Sang-whan Chang, Woo-Yeong Cho, Jei-Hwan Yoo, Young-Hyun Jun
Published in 2011 IEEE International Solid-State Circuits Conference (01.02.2011)
Published in 2011 IEEE International Solid-State Circuits Conference (01.02.2011)
Get full text
Conference Proceeding
BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel
JANG, Young-Chan, CHUNG, Hoeju, LEE, Yun-Sang, KIM, Woo-Seop, LEE, Jung-Bae, YOO, Jeihwan, KIM, Changhyun, CHOI, Youngdon, PARK, Hwanwook, KIM, Jaekwan, LIM, Soouk, SUNWOO, Jung, PARK, Moon-Sook, KIM, Hyung-Seuk, KIM, Sang-Yun
Published in IEEE journal of solid-state circuits (01.11.2009)
Published in IEEE journal of solid-state circuits (01.11.2009)
Get full text
Journal Article
Conference Proceeding
HBM3 RAS: Enhancing Resilience at Scale
Gurumurthi, Sudhanva, Lee, Kijun, Jang, Munseon, Sridharan, Vilas, Nygren, Aaron, Ryu, Yesin, Sohn, Kyomin, Kim, Taekyun, Chung, Hoeju
Published in IEEE computer architecture letters (01.07.2021)
Published in IEEE computer architecture letters (01.07.2021)
Get full text
Journal Article
SCR-based ESD Protection for High Bandwidth DRAMs
Myounggon Kang, Ki-Whan Song, Hoeju Chung, Jinyoung Kim, Yeong-Taek Lee, Changhyun Kim
Published in 2007 IEEE Asian Solid-State Circuits Conference (01.11.2007)
Published in 2007 IEEE Asian Solid-State Circuits Conference (01.11.2007)
Get full text
Conference Proceeding
Channel BER Measurement for a 5.8Gb/s/pin unidirectional differential I/O for DRAM application
Hoeju Chung, Youngchan Jang, Youngdon Choi, Hwanwook Park, Jaekwan Kim, Soouk Lim, Jung Sunwoo, Moonsook Park, Hyungwsuk Kim, Sang-Yun Kim, Hyun-Kyung Kim, Su-Jin Chung, Eun-Mi Lee, Youngju Kim, Yun-Sang Lee, Woo-Seop Kim, Jung-Bae Lee, Changhyun Kim
Published in 2008 IEEE Asian Solid-State Circuits Conference (01.11.2008)
Published in 2008 IEEE Asian Solid-State Circuits Conference (01.11.2008)
Get full text
Conference Proceeding
A 512-Mb DDR3 SDRAM Prototype With $C_IO$ Minimization and Self-Calibration Techniques
Park, C., Chung, H., Lee, Y.-S., Kim, J., Lee, J., Chae, M.-S., Jung, D.-H., Choi, S.-H., Seo, S., Park, T.-S., Shin, J.-H., Cho, J.-H., Lee, S., Song, K.-W., Kim, K.-H., Lee, J.-B., Kim, C., Cho, S.-I.
Published in IEEE journal of solid-state circuits (01.04.2006)
Published in IEEE journal of solid-state circuits (01.04.2006)
Get full text
Journal Article
25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation
Tae-Young Oh, Hoeju Chung, Young-Chul Cho, Jang-Woo Ryu, Kiwon Lee, Changyoung Lee, Jin-Il Lee, Hyoung-Joo Kim, Min Soo Jang, Gong-Heum Han, Kihan Kim, Daesik Moon, Seungjun Bae, Joon-Young Park, Kyung-Soo Ha, Jaewoong Lee, Su-Yeon Doo, Jung-Bum Shin, Chang-Ho Shin, Kiseok Oh, Doohee Hwang, Taeseong Jang, Chulsung Park, Kwangil Park, Jung-Bae Lee, Joo Sun Choi
Published in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (01.02.2014)
Published in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (01.02.2014)
Get full text
Conference Proceeding
A 512-mb DDR3 SDRAM prototype with C/sub IO/ minimization and self-calibration techniques
Churoo Park, HoeJu Chung, Yun-Sang Lee, Jaekwan Kim, JaeJun Lee, Moo-Sung Chae, Dae-Hee Jung, Sung-Ho Choi, Seung-young Seo, Taek-Seon Park, Jun-Ho Shin, Jin-Hyung Cho, Seunghoon Lee, Ki-Whan Song, Kyu-Hyoun Kim, Jung-Bae Lee, Changhyun Kim, Soo-In Cho
Published in IEEE journal of solid-state circuits (01.04.2006)
Published in IEEE journal of solid-state circuits (01.04.2006)
Get full text
Journal Article
A 512-Mb DDR3 SDRAM prototype with CIO minimization and self-calibration techniques
PARK, Churoo, CHUNG, Hoeju, SHIN, Jun-Ho, CHO, Jin-Hyung, LEE, Seunghoon, SONG, Ki-Whan, KIM, Kyu-Hyoun, LEE, Jung-Bae, KIM, Changhyun, CHO, Soo-In, LEE, Yun-Sang, KIM, Jaekwan, LEE, Jaejun, CHAE, Moo-Sung, JUNG, Dae-Hee, CHOI, Sung-Ho, SEO, Seung-Young, PARK, Taek-Seon
Published in IEEE journal of solid-state circuits (01.04.2006)
Published in IEEE journal of solid-state circuits (01.04.2006)
Get full text
Conference Proceeding
Journal Article
A 512-mb DDR3 SDRAM prototype with C sub(IO) minimization and self-calibration techniques
Park, Churoo, Chung, HoeJu, Lee, Yun-Sang, Kim, Jaekwan, Lee, JaeJun, Chae, Moo-Sung, Jung, Dae-Hee, Choi, Sung-Ho, Seo, Seung-young, Park, Taek-Seon, Shin, Jun-Ho, Cho, Jin-Hyung, Lee, Seunghoon, Song, Ki-Whan, Kim, Kyu-Hyoun, Lee, Jung-Bae, Kim, Changhyun, Cho, Soo-In
Published in IEEE journal of solid-state circuits (01.01.2006)
Published in IEEE journal of solid-state circuits (01.01.2006)
Get full text
Journal Article
A 512Mbit, 3.2Gbps/pin packet-based DRAM with cost-efficient clock generation and distribution scheme
Young-Soo Sohn, Jung-Hwan Choi, In-Young Chung, HoeJu Chung, Chan-Kyoung Kim, Gyoung-Su Byun, Dae-Woon Kang, Won-Ki Park, In-Soo Park, Hong-Sun Hwang, Chang-Hyun Kim, Soo-In Cho
Published in 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525) (2004)
Published in 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525) (2004)
Get full text
Conference Proceeding
A 512 Mbit, 1.6 Gbps/pin DDR3 SDRAM prototype with C/sub 10/ minimization and self-calibration techniques
Churoo Park, HoeJu Chung, Yun-Sang Lee, Jae-Kwan Kim, Jae-Jun Lee, Moo-Sung Chae, Dae-Hee Jung, Sung-Ho Choi, Seung-young Seo, Taek-Seon Park, Jun-Ho Shin, Jin-Hyung Cho, Seunghoon Lee, Kyu-hyoun Kim, Jung-Bae Lee, Changhyun Kim, Soo-In Cho
Published in Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005 (2005)
Published in Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005 (2005)
Get full text
Conference Proceeding
A 512Mbit, 3.2Gbps/pin packet-based DRAM with cost-efficient clock generation and distribution scheme
SOHN, Young-Soo, CHOI, Jung-Hwan, KIM, Chang-Hyun, CHO, Soo-In, CHUNG, In-Young, CHUNG, Hoeju, KIM, Chan-Kyoung, BYUN, Gyoung-Su, KANG, Dae-Woon, PARK, Won-Ki, PARK, In-Soo, HWANG, Hone-Sun
Year of Publication 2003
Get full text
Year of Publication 2003
Conference Proceeding