Search Results - "CHOI HUN DAE" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

DELAY LOCKED LOOP INCLUDING REPLICA FINE DELAY CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME

DELAY LOCKED LOOP INCLUDING REPLICA FINE DELAY CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME

by CHOI HUN DAE, YOON JUNSUB
Year of Publication 16.08.2023

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Patent

CALIBRATION CIRCUIT INCLUDING COMMON NODE SHARED BY PULL-UP CALIBRATION PATH AND PULL-DOWN CALIBRATION PATH AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME

CALIBRATION CIRCUIT INCLUDING COMMON NODE SHARED BY PULL-UP CALIBRATION PATH AND PULL-DOWN CALIBRATION PATH AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME

by CHOI HUN DAE
Year of Publication 26.02.2020

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Patent

SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD OF SEMICONDUCTOR MEMORY DEVICE

SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD OF SEMICONDUCTOR MEMORY DEVICE

by CHOI HUN DAE, KIM HWAPYONG
Year of Publication 29.01.2020

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Patent

MEMORY DEVICE MEMORY SYSTEM COMPRISING THAT AND SLEW RATE CALIBRATION METHOD THEREOF

MEMORY DEVICE MEMORY SYSTEM COMPRISING THAT AND SLEW RATE CALIBRATION METHOD THEREOF

by CHOI, HUN DAE
Year of Publication 17.05.2018

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Patent

OUTPUT BUFFER CIRCUIT AND MEMORY DEVICE COMPRISING THAT

OUTPUT BUFFER CIRCUIT AND MEMORY DEVICE COMPRISING THAT

by CHOI, HUN DAE
Year of Publication 11.05.2018

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Patent

semiconductor memory device and memory system including the same

semiconductor memory device and memory system including the same

by CHOI HUN DAE, CHANG HO JUN
Year of Publication 09.02.2023

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Patent

MEMORY DEVICE MEMORY SYSTEM HAVING THE SAME AND OPERATING METHOD THEREOF

MEMORY DEVICE MEMORY SYSTEM HAVING THE SAME AND OPERATING METHOD THEREOF

by CHOI HUN DAE, CHANG HO JUN
Year of Publication 15.12.2022

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Patent

DELAY LOCKED LOOP CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE

DELAY LOCKED LOOP CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE

by KIM HWA PYONG, CHOI HUN DAE
Year of Publication 13.01.2021

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Patent

DELAY LOCKED LOOP CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

DELAY LOCKED LOOP CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

by CHOI, HUN DAE
Year of Publication 24.05.2017

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Patent

CLOCK CORRECTION CIRCUIT AND MEMORY SYSTEM COMPRISING THE CLOCK CORRECTION CIRCUIT

CLOCK CORRECTION CIRCUIT AND MEMORY SYSTEM COMPRISING THE CLOCK CORRECTION CIRCUIT

by CHOI HUN DAE, CHOI GA RAM
Year of Publication 31.05.2022

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Patent

DQ Method for training offset calibration of dataDQ receiver and memory device thereof

DQ Method for training offset calibration of dataDQ receiver and memory device thereof

by CHOI HUN DAE, GO YOUNG GIL, SUNG YOO CHANG
Year of Publication 30.01.2024

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Patent

DUTY ADJUSTMENT CIRCUIT AND DELAY LOCKED LOOP CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME

DUTY ADJUSTMENT CIRCUIT AND DELAY LOCKED LOOP CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME

by CHOI HUN DAE, CHOI GA RAM
Year of Publication 22.02.2022

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Patent

Delay circuit of delay-locked loop circuit and delay-locked loop circuit

Delay circuit of delay-locked loop circuit and delay-locked loop circuit

by CHOI HUN DAE, CHOI GA RAM
Year of Publication 11.01.2022

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Patent

Delay-locked loop circuits semiconductor memory devices and methods of operating delay-locked loop circuits

Delay-locked loop circuits semiconductor memory devices and methods of operating delay-locked loop circuits

by CHOI HUN DAE, KIM HWA PYONG
Year of Publication 24.02.2020

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Patent

SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM

SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM

by CHOI HUN DAE, JUNG JAE HUN
Year of Publication 18.06.2019

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Patent

MEMORY DEVICE INCLUDING DELAY LOCKED LOOP AND OPERATING METHOD OF MEMORY DEVICE

MEMORY DEVICE INCLUDING DELAY LOCKED LOOP AND OPERATING METHOD OF MEMORY DEVICE

by CHOI HUN DAE, JEON JUHO, JUNG HANGI
Year of Publication 18.06.2019

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Patent

SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME

SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME

by CHOI HUN DAE, JEON JU HO
Year of Publication 31.01.2020

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Patent

Memory device having command window generator

Memory device having command window generator

by KANG, SEOK YOUNG, CHOI, HUN DAE
Year of Publication 15.01.2018

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Patent

Leakage-suppressed clock-gating circuit with zigzag super cut-OFF CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-VDD lsis

Leakage-suppressed clock-gating circuit with zigzag super cut-OFF CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-VDD lsis

by MIN, Kyeong-Sik, CHOI, Hun-Dae, CHOI, H.-Y, KAWAGUCHI, Hiroshi, SAKURAI, Takayasu
Published in IEEE transactions on very large scale integration (VLSI) systems (01.04.2006)

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Journal Article

ZQ ZQ ZQ calibration method of memory device with shared ZQ pin

ZQ ZQ ZQ calibration method of memory device with shared ZQ pin

by JEON, JU HO, CHOI, HUN DAE
Year of Publication 11.06.2018

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Patent

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