A Sub-1.0V 20nm 5Gb/s/pin post-LPDDR3 I/O interface with Low Voltage-Swing Terminated Logic and adaptive calibration scheme for mobile application
Young-Chul Cho, Yong-Cheol Bae, Byoung-Mo Moon, Yoon-Joo Eom, Min-Su Ahn, Won-Young Lee, Cheong-Ryong Cho, Min-Ho Park, Young-Jin Jeon, Jin-Oh Ahn, Baek-Kyu Choi, Dan-Kyu Kang, Sang-Hyuk Yoon, Yun-Seok Yang, Kwang-Il Park, Jung-Hwan Choi, Jung-Bae Lee, Joo-Sun Choi
Published in 2013 Symposium on VLSI Circuits (01.06.2013)
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Published in 2013 Symposium on VLSI Circuits (01.06.2013)
Conference Proceeding