Search Results - "CHIDAMBARAM PR" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

Method of providing polysilicon spacer for implantation

Method of providing polysilicon spacer for implantation

by Chidambaram, PR
Year of Publication 09.01.2003

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Patent

Method of providing polysilicon spacer for implantation

Method of providing polysilicon spacer for implantation

by CHIDAMBARAM PR
Year of Publication 09.01.2003

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Patent

Standard cell architecture using double poly patterning for multi VT devices

Standard cell architecture using double poly patterning for multi VT devices

by VANG FOUA, CHIDAMBARAM PR, KAMAL PRATYUSH, PATEL PRAYAG B, SWAMYNATHAN CHETHAN, GAN CHOCK H
Year of Publication 17.12.2013

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Patent

METAL FINGER CAPACITORS WITH HYBRID METAL FINGER ORIENTATIONS IN STACK WITH UNIDIRECTIONAL METAL LAYERS

METAL FINGER CAPACITORS WITH HYBRID METAL FINGER ORIENTATIONS IN STACK WITH UNIDIRECTIONAL METAL LAYERS

by CHIDAMBARAM, PR, GE, LIXIN, CHOI, JIHONG, ZHU, JOHN J, YANG, BIN
Year of Publication 05.12.2013

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Patent

METAL FINGER CAPACITORS WITH HYBRID METAL FINGER ORIENTATIONS IN STACK WITH UNIDIRECTIONAL METAL LAYERS

METAL FINGER CAPACITORS WITH HYBRID METAL FINGER ORIENTATIONS IN STACK WITH UNIDIRECTIONAL METAL LAYERS

by CHIDAMBARAM PR, CHOI JIHONG, GE LIXIN, YANG BIN, ZHU JOHN J
Year of Publication 05.12.2013

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Patent

STANDARD CELL ARCHITECTURE USING DOUBLE POLY PATTERNING FOR MULTI VT DEVICES

STANDARD CELL ARCHITECTURE USING DOUBLE POLY PATTERNING FOR MULTI VT DEVICES

by KAMAL, PRATYUSH, CHIDAMBARAM, PR, PATEL, PRAYAG B, GAN, CHOCK H, SWAMYNATHAN, CHETHAN, VANG, FOUA
Year of Publication 20.11.2013

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Patent

Analysis, modeling and silicon correlation of low-voltage flop data retention in 28nm process technology

Analysis, modeling and silicon correlation of low-voltage flop data retention in 28nm process technology

by Datta, A., Abu-Rahma, M., Dasnurkar, S., Rasouli, H., Tamjidi, S., Ming Cai, Sengupta, S., Chidambaram, P., Thirumala, R., Kulkarni, N., Seeram, P., Bhadri, P., Patel, P., Sei Seung Yoon, Terzioglu, E.
Published in International Symposium on Quality Electronic Design (ISQED) (01.03.2013)

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Conference Proceeding

Transistor with a diffusion barrier

Transistor with a diffusion barrier

by CHIDAMBARAM PR, YANG BIN, LI XIA
Year of Publication 28.09.2016

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Patent

SEMICONDUCTOR DEVICE HAVING HIGH MOBILITY CHANNEL

SEMICONDUCTOR DEVICE HAVING HIGH MOBILITY CHANNEL

by SENGUPTA, SAMIT, NALLAPATI, GIRIDHAR, YANG, DA, CAI, MING, CHIDAMBARAM, PR, CHOI, JIHONG, YANG, BIN, TODI, RAVI MAHENDRA, GAN, CHOCK HING, ZHU, JOHN JIANHONG
Year of Publication 02.04.2015

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Patent

SEMICONDUCTOR DEVICE HAVING HIGH MOBILITY CHANNEL

SEMICONDUCTOR DEVICE HAVING HIGH MOBILITY CHANNEL

by CHIDAMBARAM PR, CHOI JIHONG, CAI MING, ZHU JOHN JIANHONG, YANG DA, NALLAPATI GIRIDHAR, GAN CHOCK HING, YANG BIN, SENGUPTA SAMIT, TODI RAVI MAHENDRA
Year of Publication 02.04.2015

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Patent

STANDARD CELL ARCHITECTURE USING DOUBLE POLY PATTERNING FOR MULTI VT DEVICES

STANDARD CELL ARCHITECTURE USING DOUBLE POLY PATTERNING FOR MULTI VT DEVICES

by KAMAL, PRATYUSH, CHIDAMBARAM, PR, PATEL, PRAYAG B, GAN, CHOCK H, SWAMYNATHAN, CHETHAN, VANG, FOUA
Year of Publication 19.07.2012

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Patent

Standard Cell Architecture Using Double Poly Patterning for Multi VT Devices

Standard Cell Architecture Using Double Poly Patterning for Multi VT Devices

by VANG FOUA, CHIDAMBARAM PR, KAMAL PRATYUSH, PATEL PRAYAG B, SWAMYNATHAN CHETHAN, GAN CHOCK H
Year of Publication 12.07.2012

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Patent

Methods, systems and structures for forming improved transistors

Methods, systems and structures for forming improved transistors

by Chidambaram, PR, Bu, Haowen
Year of Publication 17.10.2006

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Patent

System and method for improved dopant profiles in CMOS transistors

System and method for improved dopant profiles in CMOS transistors

by Chidambaram, PR, Chakravarthi, Srinivasan
Year of Publication 10.10.2006

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Patent

System and method for improved dopant profiles in CMOS transistors

System and method for improved dopant profiles in CMOS transistors

by CHIDAMBARAM PR, CHAKRAVARTHI SRINIVASAN
Year of Publication 10.10.2006

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Patent

SYSTEM AND METHOD FOR IMPROVED DOPANT PROFILES IN CMOS TRANSISTORS

SYSTEM AND METHOD FOR IMPROVED DOPANT PROFILES IN CMOS TRANSISTORS

by CHIDAMBARAM, PR, CHAKRAVARTHI, SRINIVASAN
Year of Publication 05.10.2006

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Patent

Versatile system for limiting electric field degradation of semiconductor structures

Versatile system for limiting electric field degradation of semiconductor structures

by Chidambaram, PR, Baldwin, Greg C
Year of Publication 05.09.2006

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Patent

Versatile system for limiting electric field degradation of semiconductor structures

Versatile system for limiting electric field degradation of semiconductor structures

by CHIDAMBARAM PR, BALDWIN GREG C
Year of Publication 05.09.2006

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Patent

SYSTEM AND METHOD FOR IMPROVED DOPANT PROFILES IN CMOS TRANSISTORS

SYSTEM AND METHOD FOR IMPROVED DOPANT PROFILES IN CMOS TRANSISTORS

by CHIDAMBARAM, PR, CHAKRAVARTHI, SRINIVASAN
Year of Publication 18.05.2006

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Patent

System and method for improved dopant profiles in CMOS transistors

System and method for improved dopant profiles in CMOS transistors

by CHIDAMBARAM PR, CHAKRAVARTHI SRINIVASAN
Year of Publication 11.05.2006

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Patent

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