TID and SEE Characterization of Rad-Hardened 1.2GHz PLL IP from New ST CMOS 65nm Space Technology
Malou, Florence, Gasiot, Gilles, Chevallier, Remy, Dugoujon, Laurent, Roche, Philippe
Published in 2014 IEEE Radiation Effects Data Workshop (REDW) (01.07.2014)
Published in 2014 IEEE Radiation Effects Data Workshop (REDW) (01.07.2014)
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Conference Proceeding
Soft Oxide Breakdown impact on the functionality of a 40 nm SRAM memory
Cheffah, S, Huard, V, Chevallier, R, Bravaix, A
Published in 2011 International Reliability Physics Symposium (01.04.2011)
Published in 2011 International Reliability Physics Symposium (01.04.2011)
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Conference Proceeding
Managing SRAM reliability from bitcell to library level
Huard, V, Chevallier, R, Parthasarathy, C, Mishra, A, Ruiz-Amador, N, Persin, F, Robert, V, Chimeno, A, Pion, E, Planes, N, Ney, D, Cacho, F, Kapoor, N, Kulshrestha, V, Chopra, S, Vialle, N
Published in 2010 IEEE International Reliability Physics Symposium (01.05.2010)
Published in 2010 IEEE International Reliability Physics Symposium (01.05.2010)
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Conference Proceeding
Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata
Chevallier, Remy, Encrenaz-Tiphène, Emmanuelle, Fribourg, Laurent, Xu, Weiwen
Published in Formal Modeling and Analysis of Timed Systems (2006)
Published in Formal Modeling and Analysis of Timed Systems (2006)
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Book Chapter
Conference Proceeding
Formal verification of timed VHDL programs
Bara, A, Bazargan-Sabet, P, Chevallier, R, Encrenaz, E, Ledu, D, Renault, P
Published in 2010 Forum on Specification & Design Languages (FDL 2010) (2010)
Published in 2010 Forum on Specification & Design Languages (FDL 2010) (2010)
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Conference Proceeding