High performance and reliable TO package
Lee Teck Sim, Yong Wae Chet
Published in 2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT) (01.11.2012)
Published in 2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT) (01.11.2012)
Get full text
Conference Proceeding
Stacked transistor chip package with source coupling
Yuferev, Sergey, Ng, Chee Yang, Palm, Petteri, Long, Theng Chao, Calo, Paul Armand Asentista, Maerz, Josef, Yong, Wae Chet
Year of Publication 17.09.2024
Get full text
Year of Publication 17.09.2024
Patent
Chip to chip interconnect in encapsulant of molded semiconductor package
Chiang, Chau Fatt, Saw, Khay Chwan, Macheiner, Stefan, Yong, Wae Chet
Year of Publication 31.01.2023
Get full text
Year of Publication 31.01.2023
Patent
Chip to Chip Interconnect in Encapsulant of Molded Semiconductor Package
Chiang, Chau Fatt, Saw, Khay Chwan, Macheiner, Stefan, Yong, Wae Chet
Year of Publication 16.12.2021
Get full text
Year of Publication 16.12.2021
Patent
Chip to chip interconnect in encapsulant of molded semiconductor package
Chiang, Chau Fatt, Saw, Khay Chwan, Macheiner, Stefan, Yong, Wae Chet
Year of Publication 28.09.2021
Get full text
Year of Publication 28.09.2021
Patent
Gestapeltes Transistorchip-Package mit Source-Kopplung
Yuferev, Sergey, Ng, Chee Yang, Palm, Petteri, Long, Theng Chao, Calo, Paul Armand Asentista, Maerz, Josef, Yong, Wae Chet
Year of Publication 21.04.2022
Get full text
Year of Publication 21.04.2022
Patent
Chip to Chip Interconnect in Encapsulant of Molded Semiconductor Package
Chiang, Chau Fatt, Saw, Khay Chwan, Macheiner, Stefan, Yong, Wae Chet
Year of Publication 08.10.2020
Get full text
Year of Publication 08.10.2020
Patent
STACKED TRANSISTOR CHIP PACKAGE WITH SOURCE COUPLING
PALM, Petteri, YUFEREV, Sergey, MAERZ, Josef, YONG, Wae Chet, NG, Chee Yang, LONG, Theng Chao, CALO, Paul Armand Asentista
Year of Publication 21.04.2022
Get full text
Year of Publication 21.04.2022
Patent
VERKAPSELTES, ANSCHLUSSLEITERLOSES PACKAGE MIT ZUMINDEST TEILWEISE FREILIEGENDER INNENSEITENWAND EINES CHIPTRÄGERS, ELEKTRONISCHE VORRICHTUNG, VERFAHREN ZUM HERSTELLEN EINES ANSCHLUSSLEITERLOSEN PACKAGES UND VERFAHREN ZUM HERSTELLEN EINER ELEKTRONISCHEN VORRICHTUNG
Liebl, Christoph, Tay, Bun Kian, Bemmerl, Thomas, Chan, Kuok Wai, Tay, Wee Boon, Yong, Wae Chet
Year of Publication 29.04.2021
Get full text
Year of Publication 29.04.2021
Patent
Chip to Chip Interconnect in Encapsulant of Molded Semiconductor Package
WAE CHET YONG, KHAY CHWAN ANDREW SAW, STEFAN MACHEINER, CHAU FATT CHIANG
Year of Publication 20.10.2020
Get full text
Year of Publication 20.10.2020
Patent
CHIP-ZU-CHIP-VERBINDUNG IN DER VERKAPSELUNG EINES VERGOSSENEN HALBLEITERGEHÄUSES
Saw, Khay Chwan Andrew, Chiang, Chau Fatt, Macheiner, Stefan, Yong, Wae Chet
Year of Publication 08.10.2020
Get full text
Year of Publication 08.10.2020
Patent
Leadframe Strip with Sawing Enhancement Feature
ZHOU SEE THIONG, CHET YONG WAE, YEAP LIM LAY, LI TAI CHIEW, BOON TAY WEE
Year of Publication 25.02.2016
Get full text
Year of Publication 25.02.2016
Patent