Search Results - "CHEONG, SEONG-HWEE" :: K.UTB vyhledávací portál

Investigation of Ni/Co bilayer salicidation process for sub-40 nm gate technology

by Jung, Eun Ji, Jung, Sug-Woo, Kim, Hyun-Su, Yun, Jong-Ho, Cheong, Seong Hwee, Kim, Byung Hee, Choi, Gil Heyun, Kim, Sung Tae, Chung, U-In, Moon, Joo Tae, Ryu, Byung Il
Published in Microelectronic engineering (01.12.2005)

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Investigation of Ni/Co bilayer salicidation process for sub-40nm gate technology

by Jung, Eun Ji, Jung, Sug-Woo, Kim, Hyun-Su, Yun, Jong-Ho, Cheong, Seong Hwee, Kim, Byung Hee, Choi, Gil Heyun, Kim, Sung Tae, Chung, U-In, Moon, Joo Tae, Ryu, Byung Il
Published in Microelectronic engineering (01.12.2005)

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SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL TRANSISTOR AND METHOD OF FABRICATING THE SAME

by CHOI, GYU WAN, CHEONG, SEONG HWEE, KIM, JOON, KANG, MAN SUG, NAM, KI HONG
Year of Publication 20.11.2013

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

by KIM, TAEK JUNG, PARK, YOUNG WOOK, CHEONG, SEONG HWEE, KONG, MYUNG HO, KANG, MAN SUG, PARK, HEE SOOK
Year of Publication 12.03.2014

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CAPACITOR OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

by KIM, TAE KYUN, PARK, DONG KYUN, CHEONG, SEONG HWEE, KANG, MAN SUG, PARK, HEE SOOK
Year of Publication 03.05.2012

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METHOD OF FABRICATING A SEMICONDUCTOR DEVICE

by HA, TAE HONG, CHEONG, SEONG HWEE, LEE, JUN BUM
Year of Publication 09.08.2010

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GATE STRUCTURES AND METHOD OF FORMING THE SAME

by KIM, BYUNG HEE, CHEONG, SEONG HWEE, BAEK, JONG MIN, CHA, TAE HO, PARK, HEE SOOK, CHOI, GIL HEYUN
Year of Publication 28.10.2009

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METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING BURIED WIRING

by LEE, BYUNG HAK, CHEONG, SEONG HWEE, BAEK, JONG MIN, PARK, JAE HWA, PARK, HEE SOOK, CHA, TAE HO, KIM, SU KYOUNG, CHOI, GIL HEYUN
Year of Publication 26.08.2010

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Effect of a noble annealing system on nickel silicide formation

by Sug-Woo Jung, Hyun-Su Kim, Eun-Ji Jung, Seong-Hwee Cheong, Jong-Ho Yun, Kwan-Jong Roh, Ja-Hum Ku, Gil-Heyun Choi, Sung-Tae Kim, U-In Chung, Joo-Tae Moon, Byung-Il Ryu
Published in 12th IEEE International Conference on Advanced Thermal Processing of Semiconductors, 2004. RTP 2004 (2004)

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Trap Layer Engineered FinFET NAND Flash with Enhanced Memory Window

by Ahn, Y., Choe, J.-D., Lee, J., Choi, D., Cho, E., Choi, B., Lee, S.-H., Sung, S.-K., Lee, C.-H., Cheong, S., Lee, D., Kim, S., Park, D., Ryu, B.-I.
Published in 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers (2006)

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Charge Trapping WN Nano-dots with /or without Nitride Sub-layer for FinFET FLASH Memory

by Choe, Jeong-dong, Lee, Jong Jin, Ahn, Young Joon, Lee, Se-hoon, Choi, Byung Yong, Sung, Suk Kang, Cho, Eun Suk, Kim, Seung Beom, Cheong, Seong Hwee, Lee, Choong-ho, Chung, Ilsub, Park, Kyuncharn, Park, Donggun, Ryu, Byung-il
Published in 2006 64th Device Research Conference (01.06.2006)

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Method of fabricating semiconductor device

by Lee, Jun-bum, Ha, Tae-hong, Cheong, Seong-hwee
Year of Publication 25.10.2011

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Methods of forming a gate structure

by CHOI GIL-HEYUN, CHEONG SEONG-HWEE, PARK HEE-SOOK, CHA TAE-HO, KIM BYUNG-HEE, BAEK JONG-MIN
Year of Publication 26.03.2013

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Method of fabricating semiconductor device

by HA TAE-HONG, CHEONG SEONG-HWEE, LEE JUN-BUM
Year of Publication 25.10.2011

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Method of fabricating semiconductor device having buried wiring

by CHOI GIL-HEYUN, LEE BYUNG-HAK, CHEONG SEONG-HWEE, PARK JAE-HWA, PARK HEE-SOOK, CHA TAE-HO, BAEK JONG-MIN, KIM SU-KYOUNG
Year of Publication 18.06.2013

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