A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface
Haechang Lee, Kun-Yung Ken Chang, Jung-Hoon Chun, Ting Wu, Frans, Y., Leibowitz, B., Nhat Nguyen, Chin, T.J., Kaviani, K., Shen, J., Xudong Shi, Beyene, W.T., Li, S., Navid, R., Aleksic, M., Lee, F.S., Quan, F., Zerbe, J., Perego, R., Assaderaghi, F.
Published in IEEE journal of solid-state circuits (01.04.2009)
Published in IEEE journal of solid-state circuits (01.04.2009)
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Conference Proceeding
A 0.4-mW/Gb/s Near-Ground Receiver Front-End With Replica Transconductance Termination Calibration for a 16-Gb/s Source-Series Terminated Transceiver
Kaviani, K., Amirkhany, A., Huang, C., Phuong Le, Beyene, W. T., Madden, C., Saito, K., Sano, K., Murugan, V. I., Kun-Yung Ken Chang, Yuan, X. C.
Published in IEEE journal of solid-state circuits (01.03.2013)
Published in IEEE journal of solid-state circuits (01.03.2013)
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Journal Article
A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface
Kaviani, K., Ting Wu, Wei, J., Amirkhany, A., Jie Shen, Chin, T. J., Thakkar, C., Beyene, W. T., Chan, N., Chen, C., Bing Ren Chuang, Dressler, D., Gadde, V. P., Hekmat, M., Ho, E., Huang, C., Phuong Le, Mahabaleshwara, Madden, C., Mishra, N. K., Raghavan, L., Saito, K., Schmitt, R., Secker, D., Xudong Shi, Fazeel, S., Srinivas, G. S., Zhang, S., Tran, C., Vaidyanath, A., Vyas, K., Jain, M., Kun-Yung Ken Chang, Xingchao Yuan
Published in IEEE journal of solid-state circuits (01.04.2012)
Published in IEEE journal of solid-state circuits (01.04.2012)
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Conference Proceeding
A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface
Amirkhany, Amir, Wei, Jason, Mishra, Navin Kumar, Jie Shen, Beyene, Wendemagegnehu T., Chen, Catherine, Chin, T. J., Dressier, Deborah, Huang, Charlie, Gadde, Vijay P., Hekmat, Mohammad, Kaviani, Kambiz, Hai Lan, Phuong Le, Mahabaleshwara, Madden, Chris, Mukherjee, Sanku, Raghavan, Leneesh, Saito, Keisuke, Secker, Dave, Sendhil, Arul, Schmitt, Ralf, Fazeel, Shuaeb, Srinivas, Gundlapalli Shanmukha, Ting Wu, Chanh Tran, Vaidyanath, Arun, Vyas, Kapil, Ling Yang, Jain, Manish, Chang, Kun-Yung Ken, Xingchao Yuan
Published in IEEE journal of solid-state circuits (01.04.2012)
Published in IEEE journal of solid-state circuits (01.04.2012)
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Conference Proceeding
A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs
Chang, K.-Y.K., Wei, J., Huang, C., Li, S., Donnelly, K., Horowitz, M., Yingxuan Li, Sidiropoulos, S.
Published in IEEE journal of solid-state circuits (01.05.2003)
Published in IEEE journal of solid-state circuits (01.05.2003)
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