A systolic parallel multiplier over GF(3/sup m/) using neuron-MOS DLC [down-literal circuit]
BYOUNG HEE YOON, SUNG IL HAN, CHOI, Young-Hee, HWANG, Jong-Hak, SEONG, Hyeon-Kyeong, HEUNG SOO KIM
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
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A study on the constructions of MOVAGs based on algorithm for multiple-valued logic function manipulation and the circuit design using T-gate
Byoung-Hee Yoon, Jae-Suk Choi, Jong-Hak Hwang, Heung-Soo Kim
Published in Proceedings of IEEE. IEEE Region 10 Conference. TENCON 99. 'Multimedia Technology for Asia-Pacific Information Infrastructure' (Cat. No.99CH37030) (1999)
Published in Proceedings of IEEE. IEEE Region 10 Conference. TENCON 99. 'Multimedia Technology for Asia-Pacific Information Infrastructure' (Cat. No.99CH37030) (1999)
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