A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 μs and tR = 4 μs
Kouchi, Toshiyuki, Kakoi, Mami, Kumazaki, Noriyasu, Sugahara, Akio, Imamoto, Akihiro, Kajiyama, Yasufumi, Terada, Yuri, Sanad, Bushnaq, Kanagawa, Naoaki, Kodama, Takuyo, Fukuda, Ryo, Komai, Hiromitsu, Asaoka, Norichika, Ohnishi, Hidekazu, Isomura, Ryosuke, Handa, Takaya, Yamamoto, Kensuke, Ishizaki, Yuki, Deguchi, Yoko, Okuyama, Atsushi, Sato, Junichi, Yabe, Hiroki, Hsu, Hua-Ling Cynthia, Yoshihara, Masahiro
Published in IEEE journal of solid-state circuits (01.01.2021)
Published in IEEE journal of solid-state circuits (01.01.2021)
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Journal Article
A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology
Maejima, Hiroshi, Kanda, Kazushige, Fujimura, Susumu, Takagiwa, Teruo, Ozawa, Susumu, Sato, Jumpei, Shindo, Yoshihiko, Sato, Manabu, Kanagawa, Naoaki, Musha, Junji, Inoue, Satoshi, Sakurai, Katsuaki, Morozumi, Naohito, Fukuda, Ryo, Shimizu, Yuui, Hashimoto, Toshifumi, Xu Li, Shimizu, Yuuki, Abe, Kenichi, Yasufuku, Tadashi, Minamoto, Takatoshi, Yoshihara, Hiroshi, Yamashita, Takahiro, Satou, Kazuhiko, Sugimoto, Takahiro, Kono, Fumihiro, Abe, Mitsuhiro, Hashiguchi, Tomoharu, Kojima, Masatsugu, Suematsu, Yasuhiro, Shimizu, Takahiro, Imamoto, Akihiro, Kobayashi, Naoki, Miakashi, Makoto, Yamaguchi, Kouichirou, Bushnaq, Sanad, Haibi, Hicham, Ogawa, Masatsugu, Ochi, Yusuke, Kubota, Kenro, Wakui, Taichi, Dong He, Weihan Wang, Minagawa, Hiroe, Nishiuchi, Tomoko, Hao Nguyen, Kwang-Ho Kim, Ken Cheah, Yee Koh, Feng Lu, Ramachandra, Venky, Rajendra, Srinivas, Choi, Steve, Payak, Keyur, Raghunathan, Namas, Georgakis, Spiros, Sugawara, Hiroshi, Seungpil Lee, Futatsuyama, Takuya, Hosono, Koji, Shibata, Noboru, Hisada, Toshiki, Kaneko, Tetsuya, Nakamura, Hiroshi
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01.02.2018)
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01.02.2018)
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Conference Proceeding
SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM
SHIRAKAWA MASANOBU, AKAMINE KIMIYUKI, BUSHNAQ SANAD SALEH KHAIREDDEEN
Year of Publication 21.09.2017
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Year of Publication 21.09.2017
Patent
13.5 A 128Gb 1b/Cell 96-Word-Line-Layer 3D Flash Memory to Improve Random Read Latency with tPROG=75µs and tR=4µs
Kouchi, Toshiyuki, Kumazaki, Noriyasu, Yamaoka, Masashi, Bushnaq, Sanad, Kodama, Takuyo, Ishizaki, Yuki, Deguchi, Yoko, Sugahara, Akio, Imamoto, Akihiro, Asaoka, Norichika, Isomura, Ryosuke, Handa, Takaya, Sato, Junichi, Komai, Hiromitsu, Okuyama, Atsushi, Kanagawa, Naoaki, Kajiyama, Yasufumi, Terada, Yuri, Ohnishi, Hidekazu, Yabe, Hiroki, Hsu, Cynthia, Kakoi, Mami, Yoshihara, Masahiro
Published in 2020 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2020)
Published in 2020 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2020)
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Conference Proceeding