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Design and implementation of high-performance master/slave memory controller with microcontroller bus architecture
Ramagundam, Shashisekhar, Das, Sunil R., Morton, Scott, Biswas, Satyendra N., Groza, Voicu, Assaf, Mansour H., Petriu, Emil M.
Published in 2014 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings (01.05.2014)
Published in 2014 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings (01.05.2014)
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Conference Proceeding
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The LOTTERYBUS on-chip communication architecture
Lahiri, K., Raghunathan, A., Lakshminarayana, G.
Published in IEEE transactions on very large scale integration (VLSI) systems (01.06.2006)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.06.2006)
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Journal Article
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Network switch with multiple bus architecture
HARESKI, PATRICIA E, WITKOWSKI, MICHAEL L, MAYER, DALE J, KOTZUR, GARY B, WALKER, WILLIAM J
Year of Publication 15.12.2004
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Year of Publication 15.12.2004
Patent
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Unidirectional bus architecture for SoC applications
RAMLAOUI HUSSAM I, ZAIDI S. JAUHER A, OU MICHAEL, ADAMS LYLE E, BHAGAT ROBIN, MILLS BILLY D
Year of Publication 13.06.2006
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Year of Publication 13.06.2006
Patent
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Unidirectional bus architecture for SoC applications
RAMLAOUI HUSSAM I, ZAIDI S. JAUHER A, OU MICHAEL, ADAMS LYLE E, BHAGAT ROBIN, MILLS BILLY D
Year of Publication 05.02.2004
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Year of Publication 05.02.2004
Patent
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Network switch with multiple bus architecture
HARESKI, PATRICIA E, WITKOWSKI, MICHAEL L, MAYER, DALE J, KOTZUR, GARY B, WALKER, WILLIAM J
Year of Publication 16.06.1999
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Year of Publication 16.06.1999
Patent
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Network switch with multiple bus architecture
HARESKI, PATRICIA E, WITKOWSKI, MICHAEL L, MAYER, DALE J, KOTZUR, GARY B, WALKER, WILLIAM J
Year of Publication 22.07.1998
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Year of Publication 22.07.1998
Patent