Threshold voltage roll-up/roll-off characteristic control in sub-0.2-/spl mu/m single workfunction gate CMOS for high-performance DRAM applications
Inaba, S., Katsumata, R., Akatsu, H., Rengarajan, R., Ronsheim, P., Murthy, C.S., Sunouchi, K., Bronner, G.B.
Published in IEEE transactions on electron devices (01.02.2002)
Published in IEEE transactions on electron devices (01.02.2002)
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Journal Article
Threshold voltage roll-up/roll-off characteristic control in sub-0.2-[mu]m single workfunction gate CMOS for high-performance DRAM applications
Inaba, S, Katsumata, R, Akatsu, H, Rengarajan, R, Ronsheim, P, Murthy, C.S, Sunouchi, K, Bronner, G.B
Published in IEEE transactions on electron devices (01.02.2002)
Published in IEEE transactions on electron devices (01.02.2002)
Get full text
Journal Article
Threshold voltage roll-up/roll-off characteristic control in sub-0.2-μm single workfunction gate CMOS for high-performance DRAM applications
Inaba, S., Katsumata, R., Akatsu, H., Rengarajan, R., Ronsheim, P., Murthy, C.S., Sunouchi, K., Bronner, G.B.
Published in IEEE transactions on electron devices (01.02.2002)
Published in IEEE transactions on electron devices (01.02.2002)
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Journal Article
A 4-Mb low-temperature DRAM
Henkels, W.H., Wen, D.-S., Mohler, R.L., Franch, R.L., Bucelot, T.J., Long, C.W., Bracchitta, J.A., Cote, W.J., Bronner, G.B., Taur, Y., Dennard, R.H.
Published in IEEE journal of solid-state circuits (01.11.1991)
Published in IEEE journal of solid-state circuits (01.11.1991)
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Journal Article
A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing
Lu, N.C.-C., Bronner, G.B., Kitamura, K., Scheuerlein, R.E., Henkels, W.H., Dhong, S.H., Katayama, Y., Kirihata, T., Niijima, H., Franch, R.L., Wang, W., Nishiwaki, M., Pesavento, F.L., Rajeevakumar, T.V., Sakaue, Y., Suzuki, Y., Iguchi, Y., Yano, E.
Published in IEEE journal of solid-state circuits (01.10.1989)
Published in IEEE journal of solid-state circuits (01.10.1989)
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Journal Article
A 0.21 /spl mu/m/sup 2/ 7F/sup 2/ trench cell with a locally-open globally-folded dual bitline for 1 Gb/4 Gb DRAM
Radens, C.J., Gruening, U., Weybright, M.E., DeBrosse, J.K., Kleinhenz, R.L., Hoenigschmid, H., Thomas, A.C., Mandelman, J.A., Alsmeier, J., Bronner, G.B.
Published in 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) (1998)
Published in 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) (1998)
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Conference Proceeding
Characteristics of vertical p-channel MOSFETs for high density circuit application
Wen, D.S., Chang, W.H., Rajeevakumar, T.V., Bronner, G.B., McFarland, P.A., Lii, Y., Chen, T.C., Pesavento, F.L., Manny, M.P., Hwang, W., Dhong, S.H.
Published in 1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers (1991)
Published in 1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers (1991)
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Conference Proceeding
A Fully Planarized 0.25 /spl mu/m CMOS Technology
Wen, D.S., Chang, W.H., Lii, Y., Megdanis, A.C., McFarland, P., Bronner, G.B.
Published in 1991 Symposium on VLSI Technology (1991)
Published in 1991 Symposium on VLSI Technology (1991)
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Conference Proceeding
A novel trench DRAM cell with a vertical access transistor and buried strap (VERI BEST) for 4 Gb/16 Gb
Gruening, U., Radens, C.J., Mandelman, J.A., Michaelis, A., Seitz, M., Arnold, N., Lea, D., Casarotto, D., Knorr, A., Halle, S., Ivers, T.H., Economikos, L., Kudelka, S., Rahn, S., Tews, H., Lee, H., Divakaruni, R., Welser, J.J., Furukawa, T., Kanarsky, T.S., Alsmeier, J., Bronner, G.B.
Published in International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318) (1999)
Published in International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318) (1999)
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Conference Proceeding
A 4 Mb Low-temperature DRAM
Henkels, W.H., Wen, D.S., Mohler, R.L., Franch, R.L., Bucelot, T.J., Long, C.W., Bracchitta, J.A., Cote, W.J., Bronner, G.B., Taur, Y., Dennard, R.H.
Published in 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (1991)
Published in 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (1991)
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Conference Proceeding
Trench storage capacitors for high density DRAMs
Rajeevakumar, T.V., Lii, T., Weinberg, Z.A., Bronner, G.B., McFarland, P., Coane, P., Kwietniak, K., Megdanis, A., Stein, K.J., Cohen, S.
Published in International Electron Devices Meeting 1991 [Technical Digest] (1991)
Published in International Electron Devices Meeting 1991 [Technical Digest] (1991)
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Conference Proceeding