A GexSe1-x switch-only-memory technology through polarized atomic distribution
Liu, Zhi-Lun, Grun, Alexander, Chien, Wei-Chih, Ray, Asit, Lai, Erh-Kun, Kuo, I-Ting, Gignac, Lynne, Lavoie, Christian, BrightSky, Matt, Lung, Hsiang-Lan, Cheng, Huai-Yu
Published in Scientific reports (27.09.2024)
Published in Scientific reports (27.09.2024)
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Journal Article
Modeling of void formation in phase change memory devices
Cywar, Adam, Woods, Zachary, Kim, SangBum, BrightSky, Matt, Sosa, Norma, Zhu, Yu, Kim, Hyeong Soo, Kim, Hyung Keun, Lam, Chung, Gokirmak, Ali, Silva, Helena
Published in Solid-state electronics (01.02.2020)
Published in Solid-state electronics (01.02.2020)
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Journal Article
A Ge x Se 1-x switch-only-memory technology through polarized atomic distribution
Liu, Zhi-Lun, Grun, Alexander, Chien, Wei-Chih, Ray, Asit, Lai, Erh-Kun, Kuo, I-Ting, Gignac, Lynne, Lavoie, Christian, BrightSky, Matt, Lung, Hsiang-Lan, Cheng, Huai-Yu
Published in Scientific reports (27.09.2024)
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Published in Scientific reports (27.09.2024)
Journal Article
Performance Analysis of Spiking RBM with Measurement-Based Phase Change Memory Model
Ishii, Masatoshi, Ito, Megumi, Kim, Wanki, Kim, SangBum, Nomura, Akiyo, Okazaki, Atsuya, Okazawa, Junka, Hosokawa, Kohji, BrightSky, Matt, Haensch, Wilfried
Published in Neural Information Processing (2019)
Published in Neural Information Processing (2019)
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Book Chapter
Impact of heater configuration on Reset characteristics of PCM Mushroom cell
Chandra, Anirban, Oldiges, Phil, Chen, Ching-Tzu, Philip, Timothy M., Adusumilli, Praneet, BrightSky, Matt
Published in 2019 IEEE Albany Nanotechnology Symposium (ANS) (01.11.2019)
Published in 2019 IEEE Albany Nanotechnology Symposium (ANS) (01.11.2019)
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Conference Proceeding
(Invited) A Confined Phase Change Memory for M-Type Storage Class Memory
Kim, Wanki, BrightSky, Matt, Masuda, Takeshi, Kim, Sangbum, Bruce, Robert, Carta, Fabio, Fraczak, Gloria, Ray, Asit, Zhu, Yu, Suu, Koukou, Lam, Chung
Published in Meeting abstracts (Electrochemical Society) (01.09.2017)
Published in Meeting abstracts (Electrochemical Society) (01.09.2017)
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Journal Article
A Double-Data- Rate 2 (DDR2) Interface Phase-Change Memory with 533MB/s Read -Write Data Rate and 37.5ns Access Latency for Memory-Type Storage Class Memory Applications
Hsiang-Lan Lung, Miller, Christopher P., Chia-Jung Chen, Lewis, Scott C., Morrish, Jack, Perri, Tony, Jordan, Richard C., Hsin-Yi Ho, Tu-Shun Chen, Wei-Chih Chien, Drapa, Mark, Maffitt, Tom, Heath, Jerry, Nakamura, Yutaka, Okazawa, Junka, Hosokawa, Kohji, BrightSky, Matt, Bruce, Robert, Huai-Yu Cheng, Ray, Asit, Yung-Han Ho, Chiao-Wen Yeh, Wanki Kim, Sangbum Kim, Yu Zhu, Chung Lam
Published in 2016 IEEE 8th International Memory Workshop (IMW) (01.05.2016)
Published in 2016 IEEE 8th International Memory Workshop (IMW) (01.05.2016)
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Conference Proceeding