A Review of Low Temperature Process Modules Leading Up to the First (≤500 °C) Planar FDSOI CMOS Devices for 3-D Sequential Integration
Fenouillet-Beranger, C., Brunet, L., Batude, P., Brevard, L., Garros, X., Casse, M., Lacord, J., Sklenard, B., Acosta-Alba, P., Kerdiles, S., Tavernier, A., Vizioz, C., Besson, P., Gassilloud, R., Pedini, J.-M., Kanyandekwe, J., Mazen, F., Magalhaes-Lucas, A., Cavalcante, C., Bosch, D., Ribotta, M., Lapras, V., Vinet, M., Andrieu, F., Arcamone, J.
Published in IEEE transactions on electron devices (01.07.2021)
Published in IEEE transactions on electron devices (01.07.2021)
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Published in Solid-state electronics (01.04.2006)
Published in Solid-state electronics (01.04.2006)
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Le Royer, C., Cassé, M., Cooper, D., Andrieu, F., Weber, O., Brevard, L., Perreau, P., Damlencourt, J.-F., Baudot, S., Prévitali, B., Tabone, C., Allain, F., Scheiblin, P., Rauer, C., Figuet, C., Aulnette, C., Daval, N., Nguyen, B.-Y., Bourdelle, K.K., Gyani, J., Valenza, M.
Published in Solid-state electronics (01.11.2011)
Published in Solid-state electronics (01.11.2011)
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Morvan, S., Andrieu, F., Casse, M., Weber, O., Xu, N., Perreau, P., Hartmann, J. M., Barbe, J. C., Mazurier, J., Nguyen, P., Fenouillet-Béranger, C., Tabone, C., Tosti, L., Brevard, L., Toffoli, A., Allain, F., Lafond, D., Nguyen, B. Y., Ghibaudo, G., Boeuf, F., Faynot, O., Poiroux, T.
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Tunnel and capacitive coupling optimization in FDSOI spin-qubit devices
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Published in Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005 (2005)
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ANDRIEU, F, ERNST, T, FOURNEL, F, GHIBAUDO, G, DELEONIBUS, S, FAYNOT, O, ROZEAU, O, BOGUMILOWICZ, Y, HARTMANN, J.-M, BREVARD, L, TOFFOLI, A, LAFOND, D, GHYSELEN, B
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Novel analysis of impact of single dopants on sub-15nm channel length FDSOI NMOSFETs utilizing cryogenic measurements
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Published in 2011 Symposium on VLSI Technology - Digest of Technical Papers (01.06.2011)
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Published in 2010 IEEE International SOI Conference (SOI) (01.10.2010)
Published in 2010 IEEE International SOI Conference (SOI) (01.10.2010)
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Dual channel and strain for CMOS co-integration in FDSOI device architecture
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Published in 2009 IEEE International SOI Conference (01.10.2009)
Published in 2009 IEEE International SOI Conference (01.10.2009)
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Deleonibus, S., Mazure, C., Gaud, P., Grampeix, H., Colonna, J.P., Previtali, B., Dansas, H., Lafond, D., Jahan, C., Fenouillet-Beranger, C., Ernst, T., Denorme, S., Vandooren, A., Cluzel, J., Barbe, J.C., Allain, F., Brevard, L., Cayrefoureq, I., Ghyselen, B., Casse, M., Rouchouze, E., Buj, C., Tosti, L., Faynot, O., Rochette, F., Dupre, C., Andrieu, F.
Published in 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers (2006)
Published in 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers (2006)
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Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond
Faynot, O, Andrieu, F, Weber, O, Fenouillet-Béranger, C, Perreau, P, Mazurier, J, Benoist, T, Rozeau, O, Poiroux, T, Vinet, M, Grenouillet, L, Noel, J.-P, Posseme, N, Barnola, S, Martin, F, Lapeyre, C, Cassé, M, Garros, X, Jaud, M.-A, Thomas, O, Cibrario, G, Tosti, L, Brevard, L, Tabone, C, Gaud, P, Barraud, S, Ernst, T, Deleonibus, S
Published in 2010 International Electron Devices Meeting (01.12.2010)
Published in 2010 International Electron Devices Meeting (01.12.2010)
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Opportunities and challenges brought by 3D-sequential integration
Batude, P., Brunet, L., Fenouillet-Beranger, C., Lattard, D., Andrieu, F., Vinet, M., Brevard, L., Ribotta, M., Previtali, B., Tabone, C., Ponthenier, F., Rambal, N., Sideris, P., Garros, X., Casse, M., Theodorou, C., Sklenard, B., Lacord, J., Besson, P., Fournel, F., Kerdiles, S., Acosta-Alba, P., Mazzocchi, V., Hartmann, J-M., Mazen, F., Thuries, S., Billoint, O., Vivet, P., Sicard, G., Cibrario, G., Mouhdach, M., Giraud, B., Ribotta, CM, Lapras, V.
Published in 2021 IEEE International Interconnect Technology Conference (IITC) (06.07.2021)
Published in 2021 IEEE International Interconnect Technology Conference (IITC) (06.07.2021)
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3D sequential integration: applications and associated key enabling modules (design & technology)
Batude, P., Billoint, O., Thuries, S., Malinge, P., Fenouillet-Beranger, C., Peizerat, A., Sicard, G., Vivet, P., Reboh, S., Cavalcante, C., Brunet, L., Ribotta, M., Brevard, L., Garros, X., Frutuoso, T. Mota, Sklenard, B., Lacord, J., Kanyandekwe, J., Kerdiles, S., Sideris, P., Theodorou, C., Lapras, V., Mouhdach, M., Gaudin, G., Besnard, G., Radu, I., Ponthenier, F., Farcy, A., Jesse, E., Guyader, F., Matheret, T., Brunet, P., Milesi, F., Van-Jodin, L. Le, Sarrazin, A., Perrin, B., Moulin, C., Maitrejean, S., Alepidis, M., Ionica, I., Cristoloveanu, S., Gaillard, F., Vinet, M., Andrieu, F., Arcamone, J., Ollier, E.
Published in 2021 IEEE International Electron Devices Meeting (IEDM) (11.12.2021)
Published in 2021 IEEE International Electron Devices Meeting (IEDM) (11.12.2021)
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Mobility behavior in narrow Ω-gateFETs devices
Ritzenthaler, R., Dupre, C., Mescot, X., Faynot, O., Ernst, T., Barbe, J.-C., Jahan, C., Brevard, L., Andrieu, F., Deleonibus, S., Cristoloveanu, S.
Published in 2006 IEEE international SOI Conferencee Proceedings (01.10.2006)
Published in 2006 IEEE international SOI Conferencee Proceedings (01.10.2006)
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