Si tunnel transistors with a novel silicided source and 46mV/dec swing
Kanghoon Jeon, Wei-Yip Loh, Patel, P, Chang Yong Kang, Jungwoo Oh, Bowonder, A, Chanro Park, Park, C S, Smith, C, Majhi, P, Hsing-Huang Tseng, Jammy, R, Liu, Tsu-Jae King, Chenming Hu
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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Conference Proceeding
Demonstration of [Formula Omitted] pMOSFETs With [Formula Omitted] Channels, High [Formula Omitted], and Controlled Short Channel Effects (SCEs)
Lee, Se-Hoon, Majhi, P, Oh, Jungwoo, Sassman, B, Young, C, Bowonder, A, Loh, Wei-Yip, Choi, Kyu-Jin, Cho, Byung-Jin, Lee, Hi-Deok, Kirsch, P, Harris, H.R, Tsai, W, Datta, S, Tseng, Hsing-Huang, Banerjee, S.K, Jammy, R
Published in IEEE electron device letters (01.09.2008)
Published in IEEE electron device letters (01.09.2008)
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Journal Article
Demonstration of L \sim \hbox\ \hbox pMOSFETs With \hbox\hbox/\hbox Channels, High I/I\ (≫ \hbox \times \hbox^) , and Controlled Short Channel Effects (SCEs)
Se-Hoon Lee, Majhi, P., Jungwoo Oh, Sassman, B., Young, C., Bowonder, A., Wei-Yip Loh, Kyu-Jin Choi, Byung-Jin Cho, Hi-Deok Lee, Kirsch, P., Harris, H.R., Tsai, W., Datta, S., Hsing-Huang Tseng, Banerjee, S.K., Jammy, R.
Published in IEEE electron device letters (01.09.2008)
Published in IEEE electron device letters (01.09.2008)
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Journal Article
Demonstration of L g sim hbox 55 hbox nm pMOSFETs With hbox Si / Si 0.25 hbox Ge 0.75 / hbox Si Channels, High syntax error at token & , and Controlled Short Channel Effects (SCEs)
Lee, Se-Hoon, Majhi, P, Oh, Jungwoo, Sassman, B, Young, C, Bowonder, A, Loh, Wei-Yip, Choi, Kyu-Jin, Cho, Byung-Jin, Lee, Hi-Deok, Kirsch, P, Harris, H R, Tsai, W, Datta, S, Tseng, Hsing-Huang, Banerjee, S K, Jammy, R
Published in IEEE electron device letters (01.01.2008)
Published in IEEE electron device letters (01.01.2008)
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Journal Article
A Low Voltage Steep Turn-Off Tunnel Transistor Design
Patel, P., Kanghoon Jeon, Bowonder, A., Chenming Hu
Published in 2009 International Conference on Simulation of Semiconductor Processes and Devices (01.09.2009)
Published in 2009 International Conference on Simulation of Semiconductor Processes and Devices (01.09.2009)
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Conference Proceeding
Green Transistor - A VDD Scaling Path for Future Low Power ICs
Chenming Hu, Chou, D., Patel, P., Bowonder, A.
Published in 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) (01.04.2008)
Published in 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) (01.04.2008)
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Conference Proceeding
Prospect of tunneling green transistor for 0.1V CMOS
Chenming Hu, Patel, P, Bowonder, A, Kanghoon Jeon, Sung Hwan Kim, Wei Yip Loh, Chang Yong Kang, Jungwoo Oh, Majhi, P, Javey, A, Tsu-Jae King Liu, Jammy, R
Published in 2010 International Electron Devices Meeting (01.12.2010)
Published in 2010 International Electron Devices Meeting (01.12.2010)
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Conference Proceeding
Low-voltage green transistor using ultra shallow junction and hetero-tunneling
Bowonder, A., Patel, P., Kanghoon Jeon, Jungwoo Oh, Majhi, P., Hsing-Huang Tseng, Chenming Hu
Published in Extended Abstracts - 2008 8th International Workshop on Junction Technology (IWJT '08) (01.05.2008)
Published in Extended Abstracts - 2008 8th International Workshop on Junction Technology (IWJT '08) (01.05.2008)
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Conference Proceeding
A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size
Natarajan, S., Agostinelli, M., Akbar, S., Bost, M., Bowonder, A., Chikarmane, V., Chouksey, S., Dasgupta, A., Fischer, K., Fu, Q., Ghani, T., Giles, M., Govindaraju, S., Grover, R., Han, W., Hanken, D., Haralson, E., Haran, M., Heckscher, M., Heussner, R., Jain, P., James, R., Jhaveri, R., Jin, I., Kam, H., Karl, E., Kenyon, C., Liu, M., Luo, Y., Mehandru, R., Morarka, S., Neiberg, L., Packan, P., Paliwal, A., Parker, C., Patel, P., Patel, R., Pelto, C., Pipes, L., Plekhanov, P., Prince, M., Rajamani, S., Sandford, J., Sell, B., Sivakumar, S., Smith, P., Song, B., Tone, K., Troeger, T., Wiedemer, J., Yang, M., Zhang, K.
Published in 2014 IEEE International Electron Devices Meeting (01.12.2014)
Published in 2014 IEEE International Electron Devices Meeting (01.12.2014)
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Conference Proceeding
Low-voltage green transistor using hetero-tunneling
Bowonder, A., Patel, P., Kanghoon Jeon, Jungwoo Oh, Majhi, P., Hsing-Huang Tseng, Chenming Hu
Published in 2008 IEEE Silicon Nanoelectronics Workshop (01.06.2008)
Published in 2008 IEEE Silicon Nanoelectronics Workshop (01.06.2008)
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Conference Proceeding
Epitaxial oxide plug for strained transistors and method for forming integrated circuit structure
MURTHY, ANAND, GUHA, BISWAJEET, GHANI, TAHIR, JAMBUNATHAN, KARTHIK, BOWONDER, ANUPAMA
Year of Publication 21.11.2022
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Year of Publication 21.11.2022
Patent
Transistor with epitaxial source/drain liner for improved contact resistance
MURTHY ANAND S, BOWONDER ANUPAMA, NAM JUNKI, BOMBERGER CORY C, GHANI TAHIR
Year of Publication 27.06.2023
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Year of Publication 27.06.2023
Patent
Epitaxial oxide plug for strained transistors
MURTHY, ANAND, GUHA, BISWAJEET, GHANI, TAHIR, JAMBUNATHAN, KARTHIK, BOWONDER, ANUPAMA
Year of Publication 16.06.2019
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Year of Publication 16.06.2019
Patent
SUB-FIN LEAKAGE REDUCTION FOR TEMPLATE STRAINED MATERIALS
CEA STEPHEN, NAM JU-HYUNG, RACHMADY WILLY, BOWONDER ANUPAMA, MEHANDRU RISHABH
Year of Publication 29.12.2020
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Year of Publication 29.12.2020
Patent
Channel structures with sub-fin dopant diffusion blocking layers
MURTHY ANAND S, GUHA BISWAJEET, BOWONDER ANUPAMA, BOMBERGER CORY, CEA STEPHEN M, GHANI TAHIR
Year of Publication 07.01.2020
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Year of Publication 07.01.2020
Patent
Source or drain structure with contact etch stop layer
MURTHY ANAND S, BOWONDER ANUPAMA, GUHA BISWAJEET, MEHANDRU RISHABH, BOMBERGER CORY, GHANI TAHIR
Year of Publication 07.01.2020
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Year of Publication 07.01.2020
Patent