14.5 A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS
Sun, Xun, Boora, Akshat, Zhang, Wenbing, Pamula, Venkata Rajesh, Sathe, Visvesh
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
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Conference Proceeding
19.1 Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS
Rahman, Fahim ur, Pamula, Rajesh, Boora, Akshat, Sun, Xun, Sathe, Visvesh
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
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Conference Proceeding
UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS
Sun, Xun, Boora, Akshat, Pamula, Rajesh, Huang, Chi-Hsiang, Pena-Colaiocco, Diego, Sathe, Visvesh S.
Published in 2020 IEEE Symposium on VLSI Circuits (01.06.2020)
Published in 2020 IEEE Symposium on VLSI Circuits (01.06.2020)
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Conference Proceeding
Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS
Sun, Xun, Boora, Akshat, Pamula, Rajesh, Huang, Chi-Hsiang, Pena-Colaiocco, Diego, Sathe, Visvesh S.
Published in 2020 IEEE Symposium on VLSI Circuits (01.06.2020)
Published in 2020 IEEE Symposium on VLSI Circuits (01.06.2020)
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Conference Proceeding