Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor
Pham, D.C., Aipperspach, T., Boerstler, D., Bolliger, M., Chaudhry, R., Cox, D., Harvey, P., Harvey, P.M., Hofstee, H.P., Johns, C., Kahle, J., Kameyama, A., Keaty, J., Masubuchi, Y., Pham, M., Pille, J., Posluszny, S., Riley, M., Stasiak, D.L., Suzuoki, M., Takahashi, O., Warnock, J., Weitzel, S., Wendel, D., Yazawa, K.
Published in IEEE journal of solid-state circuits (01.01.2006)
Published in IEEE journal of solid-state circuits (01.01.2006)
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A clock distribution network for microprocessors
Restle, P.J., McNamara, T.G., Webber, D.A., Camporese, P.J., Eng, K.F., Jenkins, K.A., Allen, D.H., Rohn, M.J., Quaranta, M.P., Boerstler, D.W., Alpert, C.J., Carter, C.A., Bailey, R.N., Petrovick, J.G., Krauter, B.L., McCredie, B.D.
Published in IEEE journal of solid-state circuits (01.05.2001)
Published in IEEE journal of solid-state circuits (01.05.2001)
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A 1GHz single-issue 64b powerPC processor
Hofstee, P, Aoki, N, Boerstler, D, Coulman, P, Dhong, S, Flachs, B, Kojima, N, Kwon, O, Lee, K, Meltzer, D, Nowka, K, Park, J, Peter, J, Posluszny, S, Shapiro, M
Published in Digest of technical papers - IEEE International Solid-State Circuits Conference (01.01.2000)
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Published in Digest of technical papers - IEEE International Solid-State Circuits Conference (01.01.2000)
Journal Article
A 1.0-GHz single-issue 64-bit powerPC integer processor
Silberman, J., Aoki, N., Boerstler, D., Burns, J.L., Sang Dhong, Essbaum, A., Ghoshal, U., Heidel, D., Hofstee, P., Kyung Tek Lee, Meltzer, D., Hung Ngo, Nowka, K., Posluszny, S., Takahashi, O., Vo, I., Zoric, B.
Published in IEEE journal of solid-state circuits (01.11.1998)
Published in IEEE journal of solid-state circuits (01.11.1998)
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Journal Article
"Timing closure by design," a high frequency microprocessor design methodology
Posluszny, S., Aoki, N., Boerstler, D., Coulman, P., Dhong, S., Flachs, B., Hofstee, P., Kojima, N., Kwon, O., Lee, K., Meltzer, D., Nowka, K., Park, J., Peter, J., Silberman, J., Takahashi, O., Villarrubia, P.
Published in Annual ACM IEEE Design Automation Conference: Proceedings of the 37th conference on Design automation; 05-09 June 2000 (01.06.2000)
Published in Annual ACM IEEE Design Automation Conference: Proceedings of the 37th conference on Design automation; 05-09 June 2000 (01.06.2000)
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Conference Proceeding
Design methodology for a 1.0 GHz microprocessor
Posluszny, S., Aoki, N., Boerstler, D., Burns, J., Dhong, S., Ghoshal, U., Hofstee, P., LaPotin, D., Lee, K., Meltzer, D., Ngo, H., Nowka, K., Silberman, J., Takahashi, O., Vo, I.
Published in Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273) (1998)
Published in Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273) (1998)
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On-chip circuit for measuring multi-GHz clock signal waveforms
Jenkins, K. A., Restle, P., Wang, P. Z., Hogenmiller, D., Boerstler, D., Bucelot, T.
Published in 2013 IEEE 31st VLSI Test Symposium (VTS) (01.04.2013)
Published in 2013 IEEE 31st VLSI Test Symposium (VTS) (01.04.2013)
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Conference Proceeding
Implementation of the 65nm Cell Broadband Engine
Riley, M., Flachs, B., Dhong, S., Gervais, G., Weitzel, S., Wang, M., Boerstler, D., Bolliger, M., Keaty, J., Pille, J., Berry, R., Takahashi, O., Nishino, Y., Uchino, T.
Published in 2007 IEEE Custom Integrated Circuits Conference (01.09.2007)
Published in 2007 IEEE Custom Integrated Circuits Conference (01.09.2007)
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Conference Proceeding
A 1 GHz single-issue 64 b PowerPC processor
Hofstee, P., Aoki, N., Boerstler, D., Coulman, P., Dhong, S., Flachs, B., Kojima, N., Kwon, O., Lee, K., Meltzer, D., Nowka, K., Park, J., Peter, J., Posluszny, S., Shapiro, M., Silberman, J., Takahashi, O., Weinberger, B.
Published in 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056) (2000)
Published in 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056) (2000)
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Conference Proceeding
A 1.0 GHz single-issue 64 b powerPC integer processor
Silberman, J., Aoki, N., Boerstler, D., Burns, J., Dhong, S., Essbaum, A., Ghoshal, U., Heidel, D., Hofstee, P., Lee, K., Meltzer, D., Ngo, H., Nowka, K., Posluszny, S., Takahashi, O., Vo, I., Zoric, B.
Published in 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156) (1998)
Published in 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156) (1998)
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Conference Proceeding
A new test and characterization scheme for 10+ GHz low jitter wide band PLL
Miki, K., Boerstler, D., Hailu, E., Qi, J., Pettengill, S., Yuichi Goto
Published in Asia and South Pacific Conference on Design Automation, 2006 (2006)
Published in Asia and South Pacific Conference on Design Automation, 2006 (2006)
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Conference Proceeding
A 10+ GHz low jitter wide band PLL in 90 nm PD SOI CMOS technology
Boerstler, D., Miki, K., Hailu, E., Kihara, H., Lukes, E., Peter, J., Pettengill, S., Qi, J., Strom, J., Yoshida, M.
Published in 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525) (2004)
Published in 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525) (2004)
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Conference Proceeding
A clock distribution network for microprocessors
Restle, P.J., McNamara, T.G., Webber, D.A., Camporese, P.J., Eng, K.F., Jenkins, K.A., Allen, D.H., Rohn, M.J., Quaranta, M.P., Boerstler, D.W., Alpert, C.J., Carter, C.A., Bailey, R.N., Petrovic, J.G., Krauter, B.L., McCredie, B.D.
Published in 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103) (2000)
Published in 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103) (2000)
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