The Complementary FET (CFET) for CMOS scaling beyond N3
Ryckaert, J., Schuddinck, P., Weckx, P., Bouche, G., Vincent, B., Smith, J., Sherazi, Y., Mallik, A., Mertens, H., Demuynck, S., Bao, T. Huynh, Veloso, A., Horiguchi, N., Mocuta, A., Mocuta, D., Boemmels, J.
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Conference Proceeding
First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers
Subramanian, S., Hosseini, M., Chiarella, T., Sarkar, S., Schuddinck, P., Chan, B. T., Radisic, D., Mannaert, G., Hikavyy, A., Rosseel, E., Sebaai, F., Peter, A., Hopf, T., Morin, P., Wang, S., Devriendt, K., Batuk, D., Martinez, G. T., Veloso, A., Litta, E. Dentoni, Baudot, S., Siew, Y. K., Zhou, X., Briggs, B., Capogreco, E., Hung, J., Koret, R., Spessot, A., Ryckaert, J., Demuynck, S., Horiguchi, N., Boemmels, J.
Published in 2020 IEEE Symposium on VLSI Technology (01.06.2020)
Published in 2020 IEEE Symposium on VLSI Technology (01.06.2020)
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Conference Proceeding
Integration of a Stacked Contact MOL for Monolithic CFET
Vega-Gonzalez, Victor, Radisic, D., Chan, Bt, Choudhury, S., Wang, S., Mingardi, A., Le, Q. Toan, Decoster, H., Oniki, Y., Puttarame, P., Vandersmissen, K., Soulie, J.-P., Peter, A., Batuk, A. Sepulveda. D., Martinez, G. T., Richard, O., Boemmels, J., Biesemans, S., Dentoni, E., Horiguchi, N., Park, S., Tokei, Z.
Published in 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (11.06.2023)
Published in 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (11.06.2023)
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Conference Proceeding
Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning
Mertens, H., Hosseini, M., Chiarella, T., Zhou, D., Wang, S., Mannaert, G., Dupuy, E., Radisic, D., Tao, Z., Oniki, Y., Hikavyy, A., Rosseel, R., Mingardi, A., Choudhury, S., Gowda, P. Puttarame, Sebaai, F., Peter, A., Vandersmissen, K., Soulie, J.P., Keersgieter, A. De, Lima, L. Petersen Barbosa, Cavalcante, C., Batuk, D., Martinez, G.T., Geypen, J., Seidel, F., Paulussen, K., Favia, P., Boemmels, J., Loo, R., Wong, P., Marquez, A. Sepulveda, Chan, B.T., Mitard, J., Subramanian, S., Demuynck, S., Litta, E. Dentoni, Horiguchi, N., Samavedam, S., Biesemans, S.
Published in 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (11.06.2023)
Published in 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (11.06.2023)
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Conference Proceeding
3D Sequential Low Temperature Top Tier Devices using Dopant Activation with Excimer Laser Anneal and Strained Silicon as Performance Boosters
Vandooren, A., Wu, Z., Parihar, N., Franco, J., Parvais, B., Matagne, P., Debruyn, H., Mannaert, G., Devriendt, K., Teugels, L., Vecchio, E., Radisic, D., Rosseel, E., Hikavyy, A., Chan, B. T., Waldron, N., Mitard, J., Besnard, G., Alvarez, A., Gaudin, G., Schwarzenbach, W., Radu, I., Nguyen, B. Y., Huet, K., Tabata, T., Mazzamuto, F., Demuynck, S., Boemmels, J., Collaert, N., Horiguchi, N.
Published in 2020 IEEE Symposium on VLSI Technology (01.06.2020)
Published in 2020 IEEE Symposium on VLSI Technology (01.06.2020)
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Conference Proceeding
A Benchmark Study of Complementary-Field Effect Transistor (CFET) Process Integration Options: Comparing Bulk vs. SOI vs. DSOI starting substrates
Vincent, Benjamin, Ervin, J., Boemmels, J., Ryckaert, J.
Published in 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (14.10.2019)
Published in 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (14.10.2019)
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Conference Proceeding
Inflection points in interconnect research and trends for 2nm and beyond in order to solve the RC bottleneck
Tokei, Zs, Vega, V., Murdoch, G., O'Toole, M., Croes, K., Baert, R., Veen, M. Van der, Adelmann, C., Soulie, J. P., Boemmels, J., Wilson, C., Park, S. H., Sankaran, K., Pourtois, G., Sweerts, J., Paolillo, S., Decoster, S., Mao, M., Lazzarino, F., Versluijs, J., Blanco, V., Ercken, M., Kesters, E., Le, Q-T., Holsteyns, F., Heylen, N., Teugels, L., Devriendt, K., Struyf, H., Morin, P., Jourdan, N., Elshocht, S. Van, Ciofi, I., Gupta, A., Zahedmanesh, H., Vanstreels, K., Na, M. H.
Published in 2020 IEEE International Electron Devices Meeting (IEDM) (12.12.2020)
Published in 2020 IEEE International Electron Devices Meeting (IEDM) (12.12.2020)
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Conference Proceeding
Towards understanding intrinsic degradation and breakdown mechanisms in SiOCH low-k dielectrics
Wu, C., Li, Y., Ciofi, I., Kauerauf, Th, Bömmels, J., De Wolf, I., Tőkei, Zs, Croes, K.
Published in Journal of applied physics (14.02.2015)
Published in Journal of applied physics (14.02.2015)
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Journal Article
Current Understanding of BEOL TDDB Lifetime Models
Croes, K., Wu, C., Kocaay, D., Li, Y., Roussel, Ph, Bömmels, J., Tőkei, Zs
Published in ECS journal of solid state science and technology (01.01.2015)
Published in ECS journal of solid state science and technology (01.01.2015)
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Journal Article
Alternative integration of ultralow-k dielectrics by template replacement approach
Zhang, L., de Marneffe, J.-F, Heylen, N., Murdoch, G., Tokei, Z., Boemmels, J., De Gendt, S., Baklanov, M. R.
Published in 2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM) (01.05.2015)
Published in 2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM) (01.05.2015)
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Conference Proceeding
Optimized pore stuffing for enhanced compatibility with interconnect integration flow
de Marneffe, J.-F, Zhang, L., Rutigliani, V., Noya, G., Cao, Y., Lesniewska, A., Pedreira, O., Croes, K., Gillot, C., Tokei, Z., Boemmels, J., Baklanov, M. R.
Published in 2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM) (01.05.2015)
Published in 2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM) (01.05.2015)
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Conference Proceeding
12-EUV Layer Surrounding Gate Transistor (SGT) for Vertical 6-T SRAM: 5-nm-class Technology for Ultra-Density Logic Devices
Kim, M.-S., Harada, N., Kikuchi, Y., Boemmels, J., Mitard, J., Huynh-Bao, T., Matagne, P., Tao, Z., Li, W., Devriendt, K., Ragnarsson, L.-A., Lorant, C., Sebaai, F., Porret, C., Rosseel, E., Dangol, A., Batuk, D., Martinez-Alanis, G., Geypen, J., Jourdan, N., Sepulveda, A., Puliyalil, H., Jamieson, G., van der Veen, M., Teugels, L., El-Mekki, Z., Altamirano-Sanchez, E., Li, Y., Nakamura, H., Mocuta, D., Masuoka, F.
Published in 2019 Symposium on VLSI Technology (01.06.2019)
Published in 2019 Symposium on VLSI Technology (01.06.2019)
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Conference Proceeding
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies
Bao, T. Huynh, Yakimets, D., Ryckaert, J., Ciofi, I., Baert, R., Veloso, A., Boemmels, J., Collaert, N., Roussel, P., Demuynck, S., Raghavan, P., Mercha, A., Tokei, Z., Verkest, D., Thean, A. V-Y, Wambacq, P.
Published in 2014 44th European Solid State Device Research Conference (ESSDERC) (01.09.2014)
Published in 2014 44th European Solid State Device Research Conference (ESSDERC) (01.09.2014)
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Conference Proceeding
Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications
Vandooren, A., Wu, Z., Khaled, A., Franco, J., Parvais, B., Li, W., Witters, L., Walke, A., Peng, L., Rassoul, N., Matagne, P., Debruyn, H., Jamieson, G., Inoue, F., Devriendt, K., Teugels, L., Heylen, N., Vecchio, E., Zheng, T., Radisic, D., Rosseel, E., Vanherle, W., Hikavyy, A., Chan, B. T., Besnard, G., Schwarzenbach, W., Gaudin, G., Radu, I., Nguyen, B.-Y., Waldron, N., De Heyn, V., Demuynck, S., Boemmels, J., Ryckaert, J., Collaert, N., Mocuta, D.
Published in 2019 Symposium on VLSI Technology (01.06.2019)
Published in 2019 Symposium on VLSI Technology (01.06.2019)
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Conference Proceeding
As-grown donor-like traps in low-k dielectrics and their impact on intrinsic TDDB reliability
Tang, B.J., Croes, K., Barbarin, Y., Wang, Y.Q., Degraeve, R., Li, Y., Toledano-Luque, M., Kauerauf, T., Bömmels, J., Tőkei, Zs, De Wolf, I.
Published in Microelectronics and reliability (01.09.2014)
Published in Microelectronics and reliability (01.09.2014)
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Journal Article
Conference Proceeding
DTCO and TCAD for a 12 Layer-EUV Ultra-Scaled Surrounding Gate Transistor 6T-SRAM
Matagne, P., Nakamura, H., Kim, M.-S., Kikuchi, Y., Huynh-Bao, T., Tao, Z., Li, W., Devriendt, K., Ragnarsson, L.-A., Boemmels, J., Mallik, A., Altamirano-Sachez, E., Sebaai, F., Lorant, C., Jourdan, N., Porret, C., Mocuta, D., Harada, N., Masuoka, F.
Published in 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) (01.09.2018)
Published in 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) (01.09.2018)
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Conference Proceeding
A million wafer, virtual fabrication approach to determine process capability requirements for an industry-standard 5nm BEOL two-level metal flow
Clark, W. F., Juncker, A., Paladugu, E., Fried, D., Wilson, C. J., Pourtois, G., Gallagher, M., De Jamblinne, A., Piumi, D., Boemmels, J., Tokei, Z. S., Mocuta, D.
Published in 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) (01.09.2016)
Published in 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) (01.09.2016)
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Conference Proceeding
Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm
Weckx, P., Ryckaert, J., Putcha, V., De Keersgieter, A., Boemmels, J., Schuddinck, P., Jang, D., Yakimets, D., Bardon, M. G., Ragnarsson, L.-A, Raghavan, P., Kim, R. R., Spessot, A., Verkest, D., Mocuta, A.
Published in 2017 IEEE International Electron Devices Meeting (IEDM) (01.12.2017)
Published in 2017 IEEE International Electron Devices Meeting (IEDM) (01.12.2017)
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Conference Proceeding
First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers
Vandooren, A., Franco, J., Wu, Z., Parvais, B., Li, W., Witters, L., Walke, A., Peng, L., Deshpande, V., Rassoul, N., Hellings, G., Jamieson, G., Inoue, F., Devriendt, K., Teugels, L., Heylen, N., Vecchio, E., Zheng, T., Rosseel, E., Vanherle, W., Hikavyy, A., Mannaert, G., Chan, B. T., Ritzenthaler, R., Mitard, J., Ragnarsson, L., Waldron, N., De Heyn, V., Demuynck, S., Boemmels, J., Mocuta, D., Ryckaert, J., Collaert, N.
Published in 2018 IEEE International Electron Devices Meeting (IEDM) (01.12.2018)
Published in 2018 IEEE International Electron Devices Meeting (IEDM) (01.12.2018)
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Conference Proceeding