Timing-constrained yield-driven redundant via insertion
Jin-Tai Yan, Zhi-Wei Chen, Bo-Yi Chiang, Yu-Min Lee
Published in APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems (01.11.2008)
Published in APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems (01.11.2008)
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Conference Proceeding
Width and Timing-Constrained Wire Sizing for Critical Area Minimization
Jin-Tai Yan, Bo-Yi Chiang, Shi-Qin Huang
Published in APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems (01.12.2006)
Published in APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems (01.12.2006)
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Conference Proceeding
Yield-Driven Redundant Via Insertion Based on Probabilistic Via-Connection Analysis
Jin-Tai Yan, Bo-Yi Chiang, Zhi-Wei Chen
Published in 2006 13th IEEE International Conference on Electronics, Circuits and Systems (01.12.2006)
Published in 2006 13th IEEE International Conference on Electronics, Circuits and Systems (01.12.2006)
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Conference Proceeding
Timing-constrained redundant via insertion for yield optimization
Jin-Tai Yan, Bo-Yi Chiang, Zhi-Wei Chen
Published in 2007 IEEE Northeast Workshop on Circuits and Systems (01.08.2007)
Published in 2007 IEEE Northeast Workshop on Circuits and Systems (01.08.2007)
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Conference Proceeding
Timing-constrained yield-driven wire sizing for critical area minimization
Jin-Tai Yan, Bo-Yi Chiang, Chia-Fang Lee
Published in 2006 IEEE International Symposium on Circuits and Systems (ISCAS) (2006)
Published in 2006 IEEE International Symposium on Circuits and Systems (ISCAS) (2006)
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Conference Proceeding