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Implementation of a Novel Fault Tolerant Routing Technique for Mesh Network on Chip
by
B. P., Akshay
,
K. M., Ganesh
,
D. R., Thippeswamy
,
Bhat
,
Vishnu S
.
,
Vijayakumar, Anitha
,
Y. R., Ananda
,
Jose, John
Published in
VLSI Design and Test
(2019)
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computer science
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double faults
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router micro-architecture
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