Search Results - "Bhalerao, Abhijeet" :: K.UTB vyhledávací portál

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EPWR PARTIAL BAD BLOCK DETECTION AND RE-USE USING EPWR FOR BLOCK BASED ARCHITECTURES

by KOCHAR MRINAL, SAGDEO PIYUSH, MCAULEY DEREK, BHALERAO ABHIJEET
Year of Publication 02.05.2017

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Patent

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ACUTE AND SUBACUTE MODELS OF INFLAMMATION OF NYCTANTHES ARBOR TRISTIS AND MAHARASNADI GHAN

by Bhalerao, Abhijeet R., Desai, Sandhya K., Serathia, Bhavin R., Vartak, Kaustubh M., Doshi, Gaurav M.
Published in International journal of pharmacological research (01.10.2011)

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Journal Article

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Systems and methods for expediting design of physical components through use of computationally efficient virtual simulations

by Singh, Samrendra K, Brokaw, Andrew, Tamamidis, Panos, Bhalerao, Abhijeet
Year of Publication 03.01.2023

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Patent

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Systems and methods for expediting design of physical components through use of computationally efficient virtual simulations

by Singh, Samrendra K, Brokaw, Andrew, Tamamidis, Panos, Bhalerao, Abhijeet
Year of Publication 05.04.2022

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Patent

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SYSTEMS AND METHODS FOR EXPEDITING DESIGN OF PHYSICAL COMPONENTS THROUGH USE OF COMPUTATIONALLY EFFICIENT VIRTUAL SIMULATIONS

by Singh, Samrendra K, Brokaw, Andrew, Tamamidis, Panos, Bhalerao, Abhijeet
Year of Publication 15.10.2020

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Patent

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SYSTEMS AND METHODS FOR EXPEDITING DESIGN OF PHYSICAL COMPONENTS THROUGH USE OF COMPUTATIONALLY EFFICIENT VIRTUAL SIMULATIONS

by Singh, Samrendra K, Brokaw, Andrew, Tamamidis, Panos, Bhalerao, Abhijeet
Year of Publication 15.10.2020

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Patent

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System, method and apparatus for preventing data loss due to memory defects using latches

by Kochar, Mrinal, Lee, Aaron, Bhalerao, Abhijeet
Year of Publication 29.05.2018

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Patent

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System, Method and Apparatus for Preventing Data Loss Due to Memory Defects Using Latches

by Lee Aaron, Bhalerao Abhijeet, Kochar Mrinal
Year of Publication 01.09.2016

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Patent

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System, method and apparatus for preventing data loss due to memory defects using latches

by KOCHAR MRINAL, BHALERAO ABHIJEET, LEE AARON
Year of Publication 21.06.2016

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Patent

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MECHANICAL STOP FOR QUICK HITCH LATCH ENGAGEMENT

by Zurn, Daniel J, Bhalerao, Abhijeet R, Rasset, John T, Carlson, Nathan J
Year of Publication 16.01.2020

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Patent

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Adaptive EPWR (enhanced post write read) scheduling

by KOCHAR MRINAL, SAGDEO PIYUSH, BHALERAO ABHIJEET
Year of Publication 12.01.2016

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Patent

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SYSTEM, METHOD AND APPARATUS FOR PREVENTING DATA LOSS DUE TO MEMORY DEFECTS USING LATCHES

by KOCHAR MRINAL, BHALERAO ABHIJEET, LEE AARON
Year of Publication 10.12.2015

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Patent

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Partial bad block detection and re-use using EPWR for block based architectures

by Sagdeo Piyush, McAuley Derek, Kochar Mrinal, Bhalerao Abhijeet
Year of Publication 31.10.2017

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Patent

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ADAPTIVE EPWR (ENHANCED POST WRITE READ) SCHEDULING

by KOCHAR MRINAL, SAGDEO PIYUSH, BHALERAO ABHIJEET
Year of Publication 09.04.2015

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Patent

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Initialization techniques for multi-level memory cells using multi-pass programming

by Lee Aaron, Kochar Mrinal, Bhalerao Abhijeet, Palityka Mikhail
Year of Publication 04.10.2016

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Patent

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Memory system performance configuration

by Joshi Namita, Fernandez Frederick, Yadav Preeti, Bhalerao Abhijeet, Sarana Barys
Year of Publication 13.09.2016

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Patent

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INITIALIZATION TECHNIQUES FOR MULTI-LEVEL MEMORY CELLS USING MULTI-PASS PROGRAMMING

by KOCHAR MRINAL, PALITYKA MIKHAIL, BHALERAO ABHIJEET, LEE AARON
Year of Publication 21.07.2016

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Patent

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PARTIAL BAD BLOCK DETECTION AND RE-USE USING EPWR FOR BLOCK BASED ARCHITECTURES

by SAGDEO, PIYUSH, BHALERAO, ABHIJEET, KOCHAR, MRINAL, MCAULEY, DEREK
Year of Publication 28.01.2016

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Patent

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PARTIAL BAD BLOCK DETECTION AND RE-USE USING EPWR FOR BLOCK BASED ARCHITECTURES

by KOCHAR MRINAL, SAGDEO PIYUSH, MCAULEY DEREK, BHALERAO ABHIJEET
Year of Publication 21.01.2016

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Patent

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Data folding in 3D nonvolatile memory

by Lee Aaron, Baran Ivan, Bhalerao Abhijeet, Kochar Mrinal, Palityka Mikhail, Ng Yew Yin, Ea Dennis S
Year of Publication 02.01.2018

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Patent

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